FUJITSU MB91460 SERIES FR60 - Manual (Page 415)

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Chapter 29 MPU / EDSU
3.Break Functions
3. Break Functions
3.1 Instruction address break
The instruction address point break is the most basic break that occurs when an instruction is fetched at the address
specified by the break address data registers BAD[3:0]. Setting the CTC[1:0] bits of the control register BCR0 to ’00’
provides this mode. The bits EP[3:0] in BCR0 enable the break points.
Up to 4 instruction breakpoints from channels 0 to 3 can be set. All instruction break events are ORed into instruction
break exception requests to the CPU.
2 of the break address registers can operate as mask registers (BAD0, BAD2) for masking the instruction address
which is being fetched. Mask register BAD0 can be assigned either to BAD1 (same channel) or BAD2/3 (opposite
channel), mask register BAD2 can be assigned either to BAD3 or BAD0/1.
Normally Instruction break address and mask information reside in the same channel. So BAD3 contains the in-
struction break address and BAD2 the address mask information. The channel is enabled with EP3. The same ap-
plies for channel BAD1 (address), BAD0 (mask) and EP1 (enable).
But some cases require enabling point 2 (EP2) or the range function (ER1). Then BAD2 holds Instruction Address
information and could not carry the address mask. In that cases (when EP2 or ER1 are set) the mask information
is taken from the opposite BAD0 register. The same applies for EP0 and ER0 - which enables the use of the oppo-
site BAD2 register for the mask information.
Example: CTC 00 Type: Instruction Address Break
EP1 1 Enable break point address BAD1
EM0 1 Set mask BAD0 for break address BAD1
BAD1 0x12345678 Set break address
BAD0 0x00000FFF Set break mask
Break occurs at 0x12345000 to 0x12345FFF
On break at BAD[3:0] the respective flags BD[3:0] in the break interrupt request register BIRQ will be set to ’1’. They
have to be reset by software in the instruction break routine.
Channels 0 and 1 (BAD0, BAD1) can be set up to function as address range match. Setting the ER0 bit of the control
register BCR0 to ’1’ provides this mode. BAD0 is the lower address and BAD1 is the upper address for address
comparison. In this mode the mask register BAD2 will mask both channels 0 and 1, if the mask feature is enabled
by EM0 = ’1’.
Alternatively channels 2 and 3 (BAD2, BAD3) can be set up to function as address range match. Setting the ER1
bit of the control register BCR0 to ’1’ provides this mode. BAD2 is the lower address and BAD3 is the upper address
for address comparison. In this mode the mask register BAD0 will mask both channels 2 and 3, if the mask feature
is enabled by EM1 = ’1’.
Example: CTC 00 Type: Instruction Address Break
EP0 1 Enable break point on BAD0
EP1 1 Enable break point on BAD1
ER0 1 Enable address range function on BAD0, BAD1
EM0 1 Enable address mask function on BAD0, BAD1
BAD0 0x12345200 Set lower break address
BAD1 0x12345300 Set upper break address
BAD2 0xF0000000 Set break mask