FUJITSU MB91460 SERIES FR60 - Manual (Page 362)

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Chapter 26 DMA Controller
2.DMA Controller (DMAC) Registers
[Bit 25] SADM (Source-ADdr. Count-Mode select)*: Transfer source address count mode specification
This bit specifies the address processing of the transfer source address of the corresponding channel in each
transfer operation.
An address increment is added or an address decrement is subtracted after each transfer operation according
to the specified transfer source address count width (SASZ). When the transfer is completed, the next access
address is written to the corresponding address register (DMASA).
As a result, the transfer source address register is not updated until DMA transfer is completed.
To make the address always the same, specify 0 or 1 for this register and make the address count width
(SAAZ and DASZ) equal to 0.
• When reset: Initialized to 0.
• This bit is readable and writable.
[Bit 24] DADM (Destination-ADdr. Count-Mode select)*: Transfer destination address count mode
specification
This bit specifies the address processing for the transfer destination address of the corresponding channel in
each transfer operation.
An address increment is added or an address decrement is subtracted after each transfer operation according
to the specified transfer destination address count width (DASZ). When the transfer is completed, the next
access address is written to the corresponding address register (DMADA).
As a result, the transfer destination address register is not updated until the DMA transfer is completed.
To make the address always the same, specify 0 or 1 for this register and make the address count width
(SASZ, DASZ) equal to 0.
• When reset: Initialized to 0.
• This bit is readable and writable.
SADM Function
0 Increments transfer source address. (initial value)
1 Decrements the transfer source address.
DADM Function
0 Increments the transfer source address. (initial value)
1 Decrements the transfer source address.