FUJITSU MB91460 SERIES FR60 - Manual (Page 231)

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Chapter 14 PLL Interface
7.Caution
7. Caution
When using the clock auto-gear function it is strongly recommended to make use of the gear up and gear
down flags (PLLCTRL.GRUP, PLLCTRL.GRDN) to evaluate the current state of this function to avoid
malfunctions in the clock system due to setting changes prior to completion.
Procedure example:
• Set the PLL interface registers (PLLDIVN, PLLDIVM, PLLDIVG, PLLMULG) according to the selected
frequency and gear duration
• Switch on the PLL (CLKR.PLL1EN=’1’)
• If you want to receive interrupts after gearing up or down, also enable the corresponding interrupt
enables (PLLCTRL.IEUP, PLLCTRL.IEDN)
• Wait for the PLL stabilization time
• Set the base clock division registers (DIV0R, DIV1R)
• Switch the clock source to the PLL (CLKR.CLKS “00”-> “10”)
• Wait for the PLLCTRL.GRUP gear up flag (either by polling or by interrupt) before switching the
clock source back to oscillation or confirm the setting of PLLCTRL.GRUP=’1’ before changing bits in
the CLKR register
• Switch the clock source to Oscillator (CLKR.CLKS “10”-> “00”)
• Wait for PLLCTRL.GRDN gear down flag (either by polling or by interrupt) before switching the clock
source back to PLL or confirm the setting of PLLCTRL.GRDN=’1’ before changing bits in the CLKR
register
• Switch off the PLL (CLKR.PLL1EN=’0’)