FUJITSU MB91460 SERIES FR60 - Manual (Page 247)

231
Chapter 16 Clock Supervisor
4.Operation Modes
■
Disabling the RC-oscillator and the clock supervisors
The initial point of this scenario is that the RC-oscillator and main clock or sub-clock supervisor is enabled.
• The RC-oscillator can be disabled by setting bit RCE (bit 4 of CSVCR) to ’0’. First disable the main clock and
sub-clock supervisor. Do not disable the RC-oscillator while either the main clock or sub-clock supervisor is
still enabled. Then check that both SM and MM (bit 5 and bit 6 of CSVCR) are still ’0’. Disable the RC-
oscillator by setting RCE to ’0’. If either SM or MM bit is ’1’, RCE must not be set to ’0’.
• The main clock supervisor is disabled by setting MSVE (bit 3 of CSVCR) to ’0’.
• The sub-clock supervisor is disabled by setting SSVE (bit 2 of CVSVR) to ’0’.
Figure 4-6 Timing Diagram: Disabling the RC-oscillator and the clock supervisors
PONR
MCLK
SCLK
RC_CLK
OSC_STAB
MSVE
MSEN
SSVE
SSEN
MCLK_STBY
SCLK_STBY
TO_MCLK
TO_SCLK
EXT_RST
EXT_RST_OUT
MCLK_OUT
SCLK_OUT
MCLK_MISSING
SCLK_MISSING
SRST
RCE