FUJITSU MB91460 SERIES FR60 - Manual (Page 304)

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Chapter 21 Hardware Watchdog Timer
5.Caution
5. Caution
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Software disabling is not possible
The watchdog timer starts counting immediately after reset (release of INITX). Software cannot stop
the counting.
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Hardware disabling is only possible on the evaluation device MB91V460
The watchdog timer can be permanently disabled by setting the corresponding jumper of the
evaluation board (this is not possible on flash devices with this watchdog timer). So always ensure
correct configuration of the evalution system to reflect the behaviour of the flash device.
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Postponement of reset
In order to postpone the watchdog reset, the clearing of the watchdog timer is necessary. Whenever the CL bit
of register is set to ‘0’ (there is no minimum writing limitation), the timer is cleared and the occurrance of reset
is postponed. Just writing to the register without setting CL to ‘0’ does not clear the timer.
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Timer stop and clear
In modes where the CPU does not work (SLEEP, STOP or RTC mode), the timer is cleared first then the
counting is stopped.
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During DMA transfer
During DMA transfer between D-bus modules, the writing ‘0’ to CL bit is not possible. Thus, if the transfer time
is more than 328ms (calculated from the fastest frequency of the RC oscillator as minimum period), a reset
occurs.
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Duration setting
Unlike on MB91V460 Rev.A it is possible on flash devices to elongate the duration of the watchdog reset.
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RC clock frequency
Unlike on MB91V460 Rev.A it is possible on flash devices to change the RC clock frequency to 2MHz. Even
though the watchdog timer is always operated with a frequency of 100kHz (10us) typical.