FUJITSU MB91460 SERIES FR60 - Manual (Page 725)

709
Chapter 34 CAN Controller
2.Register Description
■
IFx Arbitration Registers (IFxARB)
The bits of the Message Buffer registers mirror the Message Objects in the Message RAM.
MXtd MDir res Msk28-24
⇐ Bit no.
Read/write ⇒ (R/W) (R/W) (R) (R/W) (R/W) (R/W) (R/W) (R/W)
Default value
⇒ (1) (1) (1) (1) (1) (1) (1) (1)
IFx Mask 2 Register high byte
Address : Base + 0x14 H & Base + 0x44 H
15 14 13 12 11 10 9 8
IFxMSK2H
Msk23-16
⇐ Bit no.
Read/write
⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Default value
⇒ (1) (1) (1) (1) (1) (1) (1) (1)
Address : Base + 0x15 H & Base + 0x 45 H
7 6 5 4 3 2 1 0
IFxMSK2L
IFx Mask 2 Register low byte
Msk15-8
⇐ Bit no.
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Default value ⇒ (1) (1) (1) (1) (1) (1) (1) (1)
IFx Mask 1 Register high byte
Address : Base + 0x16 H & Base + 0x46 H
15 14 13 12 11 10 9 8
IFxMSK1H
Msk7-0
⇐ Bit no.
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Default value ⇒ (1) (1) (1) (1) (1) (1) (1) (1)
Address : Base + 0x17 H & Base + 0x 47 H
7 6 5 4 3 2 1 0
IFxMSK1L
IFx Mask 1 Register low byte
MsgVal Xtd Dir ID28-24
⇐ Bit no.
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Default value ⇒ (0) (0) (0) (0) (0) (0) (0) (0)
IFx Arbitration 2 Register high byte
Address : Base + 0x18 H & Base + 0x48 H
15 14 13 12 11 10 9 8
IFxARB2H
ID23-16
⇐ Bit no.
Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Default value
⇒ (0) (0) (0) (0) (0) (0) (0) (0)
Address : Base + 0x19 H & Base + 0x 49 H
7 6 5 4 3 2 1 0
IFxARB2L
IFx Arbitration 2 Register low byte