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FUJITSU MB91460 SERIES FR60 User Manual

Page 714

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698

Chapter 34 CAN Controller

2.Register Description

recovery sequence, the Error Management Counters will be reset.

(Note)

During the waiting time after the resetting of Init, each time a sequence of 11 recessive bits has
been monitored, a Bit0Error code is written to the Status Register, enabling the CPU to readily
check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the
proceeding of the busoff recovery sequence.

Status Register (STATR)

res

res

res

res

res

res

res

res

⇐ Bit no.

Read/write

(R)

(R)

(R)

(R)

(R)

(R)

(R)

(R)

Default value

(0)

(0)

(0)

(0)

(0)

(0)

(0)

(0)

Status Register high byte

Address : Base + 0x02

H

15

14

13

12

11

10

9

8

STATRH

BOff EWarnEPassRxOK TxOK

LEC

⇐ Bit no.

Read/write

(R)

(R)

(R)

(R/W) (R/W) (R/W) (R/W) (R/W)

Default value

(0)

(0)

(0)

(0)

(0)

(0)

(0)

(0)

Address : Base + 0x03

H

7

6

5

4

3

2

1

0

STATRL

Status Register low byte