FUJITSU MB91460 SERIES FR60 User Manual
Page 722
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Chapter 34 CAN Controller
2.Register Description
■
Function of the IFx Command Request Registers (IFxCREQ)
(Note)
Note: The Busy Flag can only be used in BASIC mode (see chapter
). When using the Message
RAM (BASIC=0) the hardware interface controls the access for read and write and this flag is always
read as ‘0’.
(Note)
When a Message Number that is not valid is written into the Command Request Register, the
Message Number will be transformed into a valid value and that Message Object will be transferred.
■
IFx Command Mask Register (IFxCMSK)
The control bits of the IFx Command Mask Register specify the transfer direction and select which of the IFx
Message Buffer Registers are source or target of the data transfer.
[bit15]
BUSY
Busy Flag
0
Reset to zero when read/write action has finished
1
Set to one when writing to the IFx Command Request Register
[bit14-bit8]
res
Reserved Bits
[bit5-bit0]
Message Number (for 32 message buffer CANs)
0x00
Not a valid Message Number, interpreted as 0x20.
0x01-
0x20
Valid Message Number, the Message Object in the Message RAM is selected for
data transfer.
0x21-
0x3F
Not a valid Message Number, interpreted as 0x01-0x1F.
[bit7-bit0]
Message Number (for 128 message buffer CANs)
0x00
Not a valid Message Number, interpreted as 0x80.
0x01-
0x80
Valid Message Number, the Message Object in the Message RAM is selected for
data transfer.
0x81-
0xFF
Not a valid Message Number, interpreted as 0x01-0x7F.
res
res
res
res
res
res
res
res
⇐ Bit no.
Read/write
⇒
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
Default value
⇒
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
IFx Command Mask Register high byte
Address : Base + 0x12
H &
Base + 0x42
H
15
14
13
12
11
10
9
8
IFxCMSKH
WR/RD Mask
Arb
Control
CIP
TxReq/
Data A Data B
⇐ Bit no.
Read/write
⇒
(R/W) (R/W)
(R/W)
(R/W) (R/W) (R/W)
(R/W) (R/W)
Default value
⇒
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Address : Base + 0x13
H &
Base + 0x
43
H
7
6
5
4
3
2
1
0
IFxCMSKL
IFx Command Mask Register low byte
NewDat