FUJITSU MB91460 SERIES FR60 User Manual
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Chapter 26 DMA Controller
2.DMA Controller (DMAC) Registers
[Bits 18 to 16] DSS2 to 0 (DMA Stop Status)*: Transfer stop source indication
These bits indicate a code (end code) of 3 bits that indicates the source of stopping or termination of DMA
transfer on the corresponding channel. For a list of end codes, see
A transfer stop request is set only when it is requested by a peripheral device or the external pin DSTP function is
used.
The Interrupt column indicates the type of interrupts that can occur.
•
When reset: Initialized to 000
B
.
•
These bits can be cleared by writing 000
B
to them.
•
These bits are readable and writable. Note that the only valid written value is 000.
[Bits 15 to 8] SASZ (Source Addr count SiZe)*: Transfer source address count size specification
These bits specify the increment or decrement width for the transfer source address (DMASA) of the
corresponding channel in each transfer operation. The value set by these bits becomes the address
increment/decrement for each transfer unit. The address increment/decrement conforms to the instruction in
the transfer source address count mode (SADM).
•
When reset: Not initialized
•
These bits are readable and writable.
Table 2-6 End Codes
DSS
Function
Interrupt
000
B
Initial value
None
x01
B
Address error (underflow/overflow)
Error
x10
B
Transfer stop request
Error
x11
B
Normal end
End
1xx
B
DMA stopped temporarily (due, for example, to
DMAH, PAUS bit, and an interrupt)
None
SASZ
Function
XX
H
Specify the increment/decrement width of the transfer source address. 0 to 255