FUJITSU MB91460 SERIES FR60 - Manual (Page 364)

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Chapter 26 DMA Controller
2.DMA Controller (DMAC) Registers
[Bit 21] DADR (Dest.-ADdr.-reg. Reload)*: Transfer destination address register reload specification
This bit controls reloading of the transfer destination address register for the corresponding channel.
If this bit enables reloading, the transfer destination address register value is restored to its initial value after
the transfer is completed.
The details of other functions are the same as those described for Bit22 (SADR).
• When reset: Initialized to 0.
• This bit is readable and writable.
[Bit 20] ERIE (ERror Interrupt Enable)*: Error interrupt output enable
This bit controls the occurrence of an interrupt for termination after an error occurs. The nature of the error that
occurred is indicated by DSS2 to 0. Note that an interrupt occurs only for specific termination causes and not
for all termination causes (Refer to bits DSS2 to 0, which are Bits 18 to 16).
• When reset: Initialized to 0.
• This bit is readable and writable.
[Bit 19] EDIE (EnD Interrupt Enable)*: End interrupt output enable
This bit controls the occurrence of an interrupt for normal termination.
• When reset: Initialized to 0.
• This bit is readable and writable.
DADR Function
0 Disables transfer destination address register reloading. (initial value)
1 Enables transfer destination address register reloading.
ERIE Function
0 Disables error interrupt request output. (initial value)
1 Enables error interrupt request output.
EDIE Function
0 Disables end interrupt request output. (initial value)
1 Enables end interrupt request output.