Motorola DSP56301 - Manual (Page 80)

Central Processor Unit (CPU) Registers
4 -6 DSP56301 User’s Manual
You can invoke the bootstrap program options (except modes 0 and 8) at any time by setting
the MA, MB, MC, and MD bits in the OMR and jumping to the bootstrap program entry
point, $FF0000. Software can set the mode selection bits directly in the OMR. Bootstrap
modes 1–7 and 9–F select different specific bootstrap loading source devices. For the
bootstrap program to execute correctly in these modes, you must use the following data
sequence when downloading the user program through an external port:
1. Three bytes that specify the number of (24-bit) program words to be loaded
2. Three bytes that specify the (24-bit) start address where the user program loads in the
DSP56301 program memory
3. The user program (three bytes for each 24-bit program word)
Note: The three bytes for each data sequence are loaded least significant byte first.
When the bootstrap program finishes loading the specified number of words, it jumps to the
specified starting address and executes the loaded program.
4.3 Central Processor Unit (CPU) Registers
There are two CPU registers that must be configured to initialize operation. The Status
Register (SR) selects various arithmetic processing protocols and contains several status
reporting flag bits. The Operating Mode Register (OMR) configures several system operating
modes and characteristics.
4.3.1 Status Register (SR)
The Status Register (SR) (Figure 4-1) is a 24-bit register that indicates the current system
state of the processor and the results of previous arithmetic computations. The SR is pushed
onto the system stack when program looping is initialized or a JSR is performed, including
long interrupts. The SR consists of the following three special-purpose 8-bit control registers:
n Extended Mode Register (EMR) (SR[23–16]) and Mode Register (MR) (SR[15–8])
—These special-purpose registers define the current system state of the processor. The
bits in both registers are affected by hardware reset, exception processing, ENDDO
(end current DO loop) instructions, RTI (return from interrupt) instructions, and TRAP
instructions. In addition, the EMR bits are affected by instructions that specify SR as
their destination (for example, DO FOREVER instructions, BRKcc instructions, and
MOVEC). During hardware reset, all EMR bits are cleared. The MR register bits are
affected by DO instructions, and instructions that directly reference the MR (for
example, ANDI, ORI, or instructions, such as MOVEC, that specify SR as the
destination). During processor reset, the interrupt mask bits are set and all other bits are
cleared.