Port Control Register C (PCRC) 7-36
Port Control Register D (PCRD) 7-36
Port Data Register (PDR) 7-38
Port Data Register C (PDRC) 7-38
Port Data Register D (PDRD) 7-38
Port Direction Register (PRR) 7-37
Port Direction Register C (PRRC) 7-37
Port Direction Register D (PRRD) 7-37
prescale divider 7-16
programming model 7-14
receive data interrupt request 7-28
Receive Data Register (RX) 7-14

7-30

Receive Shift Register 7-29
receive shift register clock output 7-4
Receive Slot Mask Register (RSM)

programming sheet B-34

Receive Slot Mask Registers (RSMA and

RSMB) 7-14

7-35

reset 7-6
RX clock 7-11
RX frame sync 7-11
RX frame sync pulses active 7-11
select source of clock signal 7-22
Serial Clock (

SCK

), ESSI 7-3

Serial Control 0 (

SC00

and

SC10

) 7-4

Serial Control 1 (

SC01

and

SC11

) 7-4

Serial Control 2 (

SC02

and

SC12

) 7-6

Serial Input Flag (IF0) 7-4
Serial Output Flag 0 (OF0) bit 7-4
Serial Output Flags (OF0–OF1) 7-18
Serial Receive Data (SRD) 7-3
Serial Transmit Data (STD) 7-3
signals 2-1
SPI protocol 7-2
Synchronous mode 7-4

7-11

7-13

Synchronous Serial Interface Status Register

(SSISR) 7-14

7-28

bit definitions 7-28
Receive Data Register Full (RDF) 7-28
Receiver Frame Sync Flag (RFS) 7-29
Receiver Overrun Error Flag (ROE) 7-28
Serial Input Flag 0 (IF0) 7-29
Serial Input Flag 1 (IF1) 7-29
Transmit Data Register Empty (TDE) 7-28
Transmit Frame Sync Flag (TFS) 7-29
Transmitter Underrun Error Flag (TUE) 7-28

Synchronous/Asynchronous (SYN) bit 7-11

Time Slot Register (TSR) 7-8

7-33

Transmit Data Registers (TX0–TX2) 7-14

7-33

Transmit Enable (TE) 7-18
Transmit Shift Registers 7-30
Transmit Slot Mask Register (TSM)

programming sheet B-34

Transmit Slot Mask Registers (TSMA and

TSMB) 7-14

7-33

TX clock 7-11
variable prescaler 7-16
word length frame sync 7-12
word length frame sync timing 7-12

Enhanced Synchronous Serial Interface 0 (ESSI0)

GPIO 5-6
signals 2-23

Enhanced Synchronous Serial Interface 1 (ESSI1)

GPIO 5-6
signals 2-25

Enhanced Universal Bus mode 6-15
EOM byte 4-12
ESSI 1-12
ESSI0 Interrupt Priority Level (S0L) bits 4-16
ESSI1 Interrupt Priority Level (S1L) bits 4-16
expansion memory 3-1
Extended Mode Register (EMR) 4-7

Arithmetic Saturation Mode (SM) 4-7
Cache Enable (CE) 4-8
Core Priority (CP) 4-7
DO FOREVER (FV) Flag 4-8
Rounding Mode (RM) 4-7
Sixteen-bit Arithmetic Mode (SA) 4-8

Extension (E) bit 4-11
External (

EXTAL

) clock input 2-5

external address bus 2-6
external bus control 2-6
External Bus Disable (EBD) bit 4-15
external data bus 2-6
external memory expansion port 2-6

Fast Back-to-Back Capable (FBBC) bit 6-66
frame rate divider 7-10
Frame Rate Divider Control (DC) bits 7-16
frame sync

generator 7-17
length 7-12
selection 7-11
signal 7-7

7-10

7-18

Frame Sync Length (FSL) bits 7-22
Frame Sync Polarity (FSP) bit 7-22
Frame Sync Relative Timing (FSR) bit 7-22
Framing Error Flag (FE) bit 8-17
functional signal groups 2-2