Motorola DSP56301 - Manual (Page 55)

Enhanced Synchronous Serial Interface 1
Signals/Connections 2 -25
2.9 Enhanced Synchronous Serial Interface 1
Table 2-14. Enhanced Serial Synchronous Interface 1
Signal Name Type
State During
Reset
Signal Description
SC10
PD0
Input or Output
Input or Output
Input Serial Control 0—For asynchronous mode, this signal is
used for the receive clock I/O (Schmitt-trigger input). For
synchronous mode, this signal is used either for transmitter 1
output or for serial I/O flag 0.
Port D 0—The default configuration following reset is GPIO
input PD0. When configured as PD0, signal direction is
controlled through the port directions register (PRR1). The
signal can be configured as an ESSI signal SC10 through the
port control register (PCR1).
This signal has a weak keeper to maintain the last state even
if all drivers are tri-stated.
SC11
PD1
Input/
Output
Input or Output
Input Serial Control 1—For asynchronous mode, this signal is the
receiver frame sync I/O. For synchronous mode, this signal is
used either for Transmitter 2 output or for Serial I/O Flag 1.
Port D 1—The default configuration following reset is GPIO
input PD1. When configured as PD1, signal direction is
controlled through PRR1. The signal can be configured as an
ESSI signal SC11 through PCR1.
This signal has a weak keeper to maintain the last state even
if all drivers are tri-stated.
SC12
PD2
Input/
Output
Input or Output
Input Serial Control Signal 2—For frame sync I/O. SC12 is the
frame sync for both the transmitter and receiver in
synchronous mode, and for the transmitter only in
asynchronous mode. When configured as an output, this
signal is the internally generated frame sync signal. When
configured as an input, this signal receives an external frame
sync signal for the transmitter (and the receiver in
synchronous operation).
Port D 2—The default configuration following reset is GPIO
input PD2. When configured as PD2, signal direction is
controlled through PRR1. The signal can be configured as an
ESSI signal SC12 through PCR1.
This signal has a weak keeper to maintain the last state even
if all drivers are tri-stated.