Motorola DSP56301 - Manual (Page 237)

Serial Communication Interface (SCI) 8 -1
Chapter 8
Serial Communication Interface (SCI)
The DSP56301 Serial Communication Interface (SCI) provides a full-duplex port for serial
communication with other DSPs, microprocessors, or peripherals such as modems. The SCI
interfaces without additional logic to peripherals that use TTL-level signals. With a small
amount of additional logic, the SCI can connect to peripheral interfaces that have non-TTL
level signals, such as RS-232, RS-422, and so on. This interface uses three dedicated signals:
transmit data, receive data, and SCI serial clock. It supports industry-standard asynchronous
bit rates and protocols, as well as high-speed synchronous data transmission. SCI
asynchronous protocols include a multidrop mode for master/slave operation with wake-up on
idle line and wake-up on address bit capability. This mode allows the DSP56301 to share a
single serial line efficiently with other peripherals.
The SCI consists of separate transmit and receive sections that can operate asynchronously
with respect to each other. A programmable baud rate generator supplies the transmit and
receive clocks. An enable vector and an interrupt vector are included so that the baud-rate
generator can function as a general-purpose timer when the SCI is not using it, or when the
interrupt timing is the same as that used by the SCI.
8.1 Operating Modes
The operating modes for the DSP56301 SCI are as follows:
n 8-bit synchronous (shift register mode)
n 10-bit asynchronous (1 start, 8 data, 1 stop)
n 11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop)
n 11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop)
n 11-bit multidrop asynchronous (1 start, 8 data, 1 data type, 1 stop)
This mode is used for master/slave operation with wake-up on idle line and wakeup on
address bit capability. It allows the DSP56301 to share a single serial line efficiently
with other peripherals.
These modes are selected by the SCR WD[2–0] bits. Synchronous data mode is essentially a
high-speed shift register for I/O expansion and stream-mode channel interfaces. A gated