Motorola DSP56301 - Manual (Page 299)

DSP56301 User’s Manual A -3
; Host boot program verify that the HI32 is operational by reading
; the status register (HSTR) and confirming that its value is $3.
;
; Suggested DSP-to-DSP connection:
;
; slave master
; 56301/HI32 563xx/PortA
;
; HA[10:3] <- A[10:3] ; selects HI32 (base address 00000000)
; HA[2:0] <- A[2:0] ; selects HTXR registers
; HD[24:0] <-> D[24:0] ; Data bus
; HBS_ <- BS_ ; Bus Strobe (optional, see Note1)
; HAEN <- AAx ; DMA cycle disable (AAx is active low)
; HTA -> TA_ ; Transfer Acknowledge (optional, see Note2)
; HIRQ_ -> IRQx_ ; Interrupt Request (active low, open drain)
; HWR_ <- WR_ ; Write strobe
; HRD_ <- RD_ ; Read strobe
; HRST <- system reset ; Reset (active low)
;
; Pins HP31, HP32 and HDAK_ must be tied to Vcc. Pins HP[22:20] can be
; used as GPIO pins. Pin HINTA_ can be used as software driven interrupt
; request pin.
;
; Note1: If HBS_ to BS_ connection is used, the synchronous connection of
; the HI32 is used and therefore the 563xx/master should access the
; 56301/slave as SRAM with 2 wait states. In addition the CLKOUT of
; 563xx/master should connect to EXTAL of 56301/slave, and both
; master and slave should enable the PLL. For the slave
; multiplication, division and predivision fuctors should be one to
; guarantee syncronization between master and slave.
; For asynchronous connection, HBS_ must be tied to Vcc.
;
; Note2: If HTA to HTA_ connection is not used, it is recommended that
; the HOST Processor’s boot program verify that the Host Interface
; is ready by reading the status register (HSTR) and confirming that TRDY=1
; or HTRQ=1.
;
;
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; If MD:MC:MB:MA=x100, then it loads the program RAM from the Host
; Interface programmed to operate in the PCI target (slave) mode.
;
; The HI32 bootstrap code expects first to read a 24-bit word specifying
; the number of program words, then a 24-bit word specifying the
; address to start loading the program words, and then 24-bit word for
; each program word to be loaded.
;
; The program words will be stored in contiguous PRAM memory
; locations starting at the specified starting address. After
; the program words are read, program execution starts from the same
; address where loading started.
;
; The Host Interface bootstrap load program can be stopped by setting the
; Host Flag 0 (HF0) in the HCTR register. This starts execution of the
; loaded program from the specified starting address.
;
; The HOST Processor must first configure the Host Interface as a PCI slave
; and then start writing data to the Host Interface. The HOST Processor
; must program the HCTR HTF1-HTF0 bits as 01, 10 or 11 and then