Motorola DSP56301 - Manual (Page 105)

DMA Control Registers 5–0 (DCR[5–0])
Core Configuration 4 -31
18–17 DPR[1–0] 0 DMA Channel Priority
Define the DMA channel priority relative to the other DMA channels and to the core priority if
an external bus access is required. For pending DMA transfers, the DMA controller
compares channel priority levels to determine which channel can activate the next word
transfer. This decision is required because all channels use common resources, such as the
DMA address generation logic, buses, and so forth.
DPR[1–0] Channel Priority
00 Priority level 0 (lowest)
01 Priority level 1
10 Priority level 2
11 Priority level 3 (highest)
n
If all or some channels have the same priority, then channels are activated in a
round-robin fashion—that is, channel 0 is activated to transfer one word, followed by
channel 1, then channel 2, and so on.
n
If channels have different priorities, the highest priority channel executes DMA
transfers and continues for its pending DMA transfers.
n
If a lower-priority channel is executing DMA transfers when a higher priority channel
receives a transfer request, the lower-priority channel finishes the current word
transfer and arbitration starts again.
n
If some channels with the same priority are active in a round-robin fashion and a new
higher-priority channel receives a transfer request, the higher-priority channel is
granted transfer access after the current word transfer is complete. After the
higher-priority channel transfers are complete, the round-robin transfers continue. The
order of transfers in the round-robin mode may change, but the algorithm remains the
same.
n
The DPR bits also determine the DMA priority relative to the core priority for external
bus access. Arbitration uses the current active DMA priority, the core priority defined
by the SR bits CP[1–0], and the core-DMA priority defined by the OMR bits CDP[1–0].
Priority of core accesses to external memory is as follows:
Table 4-12. DMA Control Register (DCR) Bit Definitions (Continued)
Bit
Number
Bit Name
Reset
Value
Description