Table b-1, Table b-1. guide to programming sheets – Motorola DSP56301 User Manual

Page 314

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B

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DSP56301 User’s Manual

Table B-1. Guide to Programming Sheets

Module

Programming Sheet

Page

Central

Processor

Figure B-1,

Status Register (SR)

Figure B-2,

Operating Mode Register (OMR)

IPR

Figure B-3,

Interrupt Priority Register Core (IPRC)

Figure B-4,

Interrupt Priority Register Peripherals (IPRP)

PLL

Figure B-5,

Phase-Locked Loop Control Register (PCTL)

BIU

Figure B-6,

Bus Control Register (BCR)

Figure B-7,

DRAM Control Register (DCR)

Figure B-8,

Address Attribute Registers (AAR[3–0])

DMA

Figure B-9,

DMA Control Registers 5–0 (DCR[5–0])

HI32

Figure B-10,

DSP Control Register (DCTR)

Figure B-11,

DSP PCI Control Register (DPCR)

Figure B-12,

DSP PCI Master Control Register (DPMC)

Figure B-13,

DSP PCI Address Register (DPAR)

Figure B-14,

HI32 Control Register (HCTR)

Figure B-15,

Host Command Vector Register (HCVR)

Figure B-16,

Status/Command Configuration Register (CSTR/CCMR)

Figure B-17,

Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)

Figure B-18,

Memory Space Base Address Configuration Register (CBMA)

Figure B-19,

Subsystem ID and Subsystem Vendor ID Configuration Register (CSID)

ESSI

Figure B-20,

ESSI Control Register A (CRA)

Figure B-21,

ESSI Control Register B (CRB)

Figure B-22,

ESSI Transmit and Receive Slot Mask Registers (TSM, RSM)

SCI

Figure B-23,

SCI Control Register (SCR)

Figure B-24,

SCI Clock Control Registers (SCCR)

Timers

Figure B-25,

Timer Prescaler Load Register (TPLR)

Figure B-26,

Timer Control/Status Register (TCSR)

Figure B-27,

Timer Load Registers (TLR)

GPIO

Figure B-28,

Host Data Direction and Host Data Registers (HDDR, HDR)

Figure B-29,

Port C Registers (PCRC, PRRC, PDRC)

Figure B-30,

Port D Registers (PCRD, PRRD, PDRD)

Figure B-31,

Port E Registers (PCRE, PRRE, PDRE)