Motorola DSP56301 User Manual
Page 362
Index
-6
DSP56301 User’s Manual
G
General-Purpose Input/Output (GPIO) 1-5
,
data register 6-43
direction register 6-43
ESSI0 5-6
ESSI1 5-6
HI08 5-5
Port B 2-3
Port C 5-6
Port D 5-6
Port E 5-6
SCI 5-6
timer 5-7
GPIO mode 6-13
ground (
GND
) 2-1
H
handshake flags 6-44
hardware stack 1-8
Header Type (HT[7–0]) bits 6-68
Header Type/Latency Timer Configuration Register
(CHTY/CLAT/CCLS)
Cache Line Size (CLS[7–0]) 6-69
Latency Timer (High) (LT[7–0]) 6-69
HI32 Active (HACT) bit 6-35
HI32 Control Register (HCTR)
DMA Enable (DMAE) 6-54
Host Flags 2–0 (HF[2–0]) 6-54
Host Receive Data Transfer Format (HRF[1–0]) 6-50
Host Semaphores (HS[2–0]) 6-49
Host Transmit Data Transfer Format
(HTF[1–0]) 6-51
Receive Request Enable (RREQ) 6-55
Slave Fetch Type (SFT) 6-52
Target Wait State Disable (TWSD) 6-49
Transmit Request Enable (TREQ) 6-56
HI32 Interrupt Priority Level (HPL) bits 4-16
HIRQ
pin 6-69
Host Command (HC) bit 6-61
Host Command Interrupt Enable (HCIE) bit 6-26
Host Command Pending (HCP) bit 6-37
Host Command Vector (HV[6–0]) bits 6-60
Host Command Vector Register (HCVR) 6-59
Host Command (HC) 6-61
Host Command Vector (HV[6–0]) 6-60
Host Non-Maskable Interrupt (HNMI) 6-60
Host Data Direction Register (HDDR)
programming sheet B-40
Host Data Register (HDR)
programming sheet B-40
Host Data Strobe Mode (HDSM) bit 6-25
Host DMA Request Polarity (HDRP) bit 6-24
Host Flags 2–0 (HF[2–0]) bits 6-36
Host Flags 5–3 (HF[5–3]) bits 6-26
Host Interface (HI32) 1-5
16-bit data Universal Bus mode 6-48
active PCI master 6-13
address insertion 6-4
bit manipulation instructions 6-26
block diagram 6-5
byte enable pins 6-45
Cache Line Size Configuration Register (CCLS) 6-34
Class Code/Revision ID Configuration Register
(CCCR/CRID) 6-67
PCI Device Base Class (BC[7–0]) 6-67
PCI Device Program Interface (P[17–10]) 6-67
PCI Device Sub-Class (SC[7–0]) 6-67
Revision ID (RID[7–0]) 6-67
clearing the HM bits 6-13
Configuration space accesses 6-45
core interrupts 6-4
data transfer 6-6
data transfer format converter 6-63
deadlock 6-46
Device/Vendor ID Configuration Register
(CDID/CVID) 6-64
disable PCI wait states 6-28
DMA 6-22
DMA transfers 6-42
DSP Control Register (DCTR) 6-23
Host Command Interrupt Enable (HCIE) 6-26
Host Data Strobe Mode (HDSM) 6-25
Host DMA Request Polarity (HDRP) 6-24
Host Flags 5–3 ‹HF[5–3]) 6-26
Host Interrupt A (HINT) 6-25
Host Interrupt Request Drive Control
(HIRD) 6-24
Host Interrupt Request Handshake Mode
(HIRH) 6-24
Host Read/Write Polarity (HRWP) 6-25
Host Reset Polarity (HRSP) 6-24
Host Transfer Acknowledge Polarity
(HTAP) 6-25
Slave Receive Interrupt Enable (SRIE) 6-26
Slave Transmit Interrupt Enable (STIE) 6-26
DSP Host Port GPIO Data Register (DATH) 6-43
DSP Host Port GPIO Direction Register (DIRH) 6-43
DSP Master Transmit Data Register (DTXM) 6-42
DSP PCI Address Register (DPAR) 6-33
DSP PCI Transaction Address (Low)
(AR[15–0] 6-34
PCI Bus Command (C[3–0]) 6-34
PCI Byte Enables (BE[3–0]) 6-33
DSP PCI Master Control Register (DPMC) 6-30
Data Transfer Format Control (FC[1–0]) 6-31