Motorola DSP56301 - Manual (Page 160)

HI32 DSP-Side Programming Model
6 -42 DSP56301 User’s Manual
when the host-to-DSP data path FIFO is emptied by DSP56300 core reads. The DSP56300
core can set the SRIE bit to cause a host receive data interrupt when SRRQ is set.
In 32-bit mode (DCTR[HM] = $1 with DPMC[FC] = $0 or HCTR[HTF] = $0), only the two
least significant bytes contain data. The most significant byte is read as zeroes. (See Table
6-3). Hardware, software, and personal software resets empty the host-to-DSP data path FIFO
(SRRQ and MRRQ are cleared).
6.7.8 DSP Master Transmit Data Register (DTXM)
The 24-bit wide DSP Master Transmit Data Register (DTXM) is the input stage of the master
DSP-to-host data path FIFO for DSP-to-host master data transfers in PCI mode (DCTR[HM]
= $1). The DTXM can be written if the DPSR[MTRQ] bit is set. To prevent overwriting of
previous data, data should not be written to the DTXM until DPSR[MTRQ] is set. Filling the
DTXM by DSP56300 core writes (MOVE(P) instructions or DMA transfers) clears
DPSR[MTRQ]. The DSP56300 core can set the DPCR[MTIE] bit to cause a host receive data
interrupt when DPSR[MTRQ] is set.
In PCI mode (DCTR[HM] = $1), the DSP56300 core can clear the HI32 master-to-host bus
data path and empty DTXM by setting DPCR[CLRT]. In 32-bit mode (DCTR[HM] = $1 with
DPMC[FC] = $0), only the two least significant bytes of the DTXM are transferred. (See
Table 6-3). Hardware, software and personal software resets empty the DTXM.
6.7.9 DSP Slave Transmit Data Register (DTXS)
The 24-bit wide DSP Slave Transmit Data Register (DTXS) is the input stage of the slave
DSP-to-host data path FIFO for DSP-to-host slave data transfers in PCI mode (DCTR[HM] =
$1).
The DTXS can be written if the DSR[STRQ] bit is set. To prevent overwriting of previous
data, data should not be written to the DTXS until DSR[STRQ] is set. Filling the DTXS by
DSP56300 core writes (MOVE(P) instructions or DMA transfers) clears DSR[STRQ]. The
DSP56300 core can set the STIE bit to cause a host receive data interrupt when DSR[STRQ]
is set. In 32-bit mode (DCTR[HM] = $1 with HCTR[HRF] = $0), only the two least
significant bytes of the DTXS are transferred. (See Section 6.3.2, DSP-To-Host Data Path,
on page 6-7, and Table 6-3, HI32 (PCI Master Data Transfer Formats, on page 6-8).
Hardware, software and personal software resets empty the DTXS.