Motorola DSP56301 - Manual (Page 286)

Operating Modes
9 -24 DSP56301 User’s Manual
9.3.4.2 Watchdog Toggle (Mode 10)
In Mode 10, the timer toggles an external signal after a preset period. The TIO signal is set to
the value of the INV bit.When the counter equals the value in the TCPR, TCSR[TCF] is set,
and a compare interrupt is generated if the TCSR[TCIE] bit is also set. If the TCSR[TRM] bit
is set, the counter loads with the TLR value on the next timer clock and the count resumes.
Therefore, TRM = 1 is not useful for watchdog functions. If the TCSR[TRM] bit is cleared,
the counter continues to increment on each subsequent timer clock. When a counter overflow
occurs, the polarity of the
TIO output signal is inverted. The counter is reloaded whenever the
TLR is written with a new value while the TCSR[TE] bit is set. This process repeats until the
timer is disabled. In Mode 10, internal logic preserves the
TIO value and direction for an
additional 2.5 internal clock cycles after the hardware RESET signal is asserted. This
convention ensures that a valid reset signal is generated when the TIO signal resets the
DSP56301.
Bit Settings Mode Characteristics
TC3 TC2 TC1 TC0 Mode Name Function TIO Clock
1 0 1 0 10 Toggle Watchdog Output Internal
Figure 9-19. Watchdog Toggle Mode
Mode 10 (internal clock): TRM = 0
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
TCF (Compare Interrupt if TCIE = 1)
Counter (TCR)
first event
M
0 N M 1
N
TRM = 1 is not useful for watchdog function
0 M + 1
TOF (Overflow Interrupt if TOIE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1)
N + 1
float
float
low
high
TIO can connect to the RESET pin, internal hardware preserves the TIO value and
direction for an additional 2.5 clocks to ensure a reset of valid length.
TCPR