Motorola DSP56301 - Manual (Page 12)

xii DSP56301 User’s Manual
6-8 DSP PCI Address Register (DPAR)..................................................................... 6-33
6-9 DSP Status Register (DSR) .................................................................................. 6-35
6-10 DSP PCI Status Register (DPSR)......................................................................... 6-38
6-11 DSP Host Port Direction Register (DIRH)........................................................... 6-43
6-12 DSP Host Port GPIO Data Register (DATH)....................................................... 6-43
6-13 Host Interface Control Register (HCTR) ............................................................. 6-48
6-14 Host Interface Status Register (HSTR) ................................................................ 6-56
6-15 Host Command Vector Register (HCVR)............................................................ 6-59
6-16 Device/Vendor ID Configuration Register (CDID/CVID) .................................. 6-64
6-17 Status/Command Configuration Register (CSTR/CCMR) .................................. 6-64
6-18 Class Code/Revision ID Configuration Register CCCR/CRID) .......................... 6-67
6-19 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)...... 6-68
6-20 Memory Space Base Address Configuration Register (CBMA).......................... 6-70
6-21 Subsystem ID and Subsystem Vendor ID Configuration Register (CSID).......... 6-71
6-22 Interrupt Line-Interrupt Pin Configuration Register(CILP) ................................. 6-73
7-1 ESSI Block Diagram .............................................................................................. 7-1
7-2 ESSI Control Register A(CRA)............................................................................ 7-14
7-3 ESSI Clock Generator Functional Block Diagram............................................... 7-17
7-4 ESSI Frame Sync Generator Functional Block Diagram ..................................... 7-17
7-5 ESSI Control Register B (CRB) ........................................................................... 7-18
7-6 CRB FSL0 and FSL1 Bit Operation (FSR = 0).................................................... 7-24
7-7 CRB SYN Bit Operation ...................................................................................... 7-25
7-8 CRB MOD Bit Operation..................................................................................... 7-26
7-9 Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame)........................... 7-27
7-10 Network Mode, External Frame Sync (8 Bit, 2 Words in Frame) ....................... 7-27
7-11 ESSI Status Register (SSISR) .............................................................................. 7-28
7-12 ESSI Data Path Programming Model (SHFD = 0)............................................... 7-31
7-13 ESSI Data Path Programming Model (SHFD = 1)............................................... 7-32
7-14 ESSI Transmit Slot Mask Register A (TSMA) .................................................... 7-33
7-15 ESSI Transmit Slot Mask Register B (TSMB)..................................................... 7-34
7-16 ESSI Receive Slot Mask Register A (RSMA) ..................................................... 7-35
7-17 ESSI Receive Slot Mask Register B (RSMB)...................................................... 7-35
7-18 Port Control Registers (PCRC X:$FFFFBF) (PCRD X:$FFFAF)....................... 7-36
7-19 Port Direction Registers (PRRC X:$FFFFBE) (PRRD X: $FFFFAE) ................ 7-37
7-20 Port Data Registers (PDRC X:$FFFFBD) (PDRD X: $FFFFAD) ...................... 7-38
8-1 SCI Data Word Formats (SSFTD = 1), 1 ............................................................. 8-10
8-2 SCI Data Word Formats (SSFTD = 0), 2 ............................................................. 8-11
8-3 SCI Control Register (SCR) ................................................................................. 8-12