Motorola DSP56301 - Manual (Page 127)

Data Transfer Paths
Host Interface (HI32) 6 -9
1 1 The three least significant HRXM bytes are output
left aligned and zero filled. The three most significant PCI data bytes are
written to the HTXR.
Table 6-4. Transmit Data Transfer Format
HCTR Host-to-DSP Data Transfer Format
HTF1 HTF0 PCI mode Universal Bus mode
0 0 All 32 PCI data bits are written to the HTXR as two
zero extended 16-bit words. All HD[23–0] data are written to the HTXR.
0 1 The three least significant PCI data bytes are written
to the HTXR. HD[15–0] are written to the HTXR, right aligned
and zero extended.
Table 6-3. HI32 (PCI Master Data Transfer Formats (Continued)
DPMC
Register DSP-to-PCI Host
Data Transfer Format
PCI Host-to-DSP
Data Transfer Format
FC1 FC0
HDTFC
PCI bus
DTXM
HI32
GDB/MDDB
$0
$0
HRXM
HDTFC
PCI bus
DRXR
HI32
GDB/MDDB
X
HTXR
$0
HDTFC
PCI bus
DRXR
HI32
GDB/MDDB
HTXR
$0
HDTFC
Host bus
DRXR
HI32
GDB/MDDB
HTXR
HDTFC
PCI bus
DRXR
HI32
GDB/MDDB
X
HTXR
HDTFC
Host bus
DRXR
HI32
GDB/MDDB $0
$0
HTXR
$0
$0