Motorola DSP56301 - Manual (Page 124)

Data Transfer Paths
6 -6 DSP56301 User’s Manual
DMA controllers, or standard peripheral buses (for example, ISA/EISA) because the interface
appears to the host as static RAM.
A host command feature enables the host processor to issue vectored interrupt requests to the
DSP56300 core. Writing to a vector address register in the HI32, the host can select any one
of 128 DSP56300 core interrupt routines to execute. This flexibility allows the host
programmer to execute up to 128 pre-programmed functions inside the DSP. For example,
host exceptions can allow the host processor to read or write DSP registers, X, Y, or program
memory locations, force exception handlers (for example, SSI, Timer,
IRQA , IRQB exception
routines), and perform control and debugging operations if exception routines are
implemented in the DSP to perform these tasks. The host processor can also generate
non-maskable interrupt requests to the DSP56300 core using the host commands.
6.3 Data Transfer Paths
The master data transfer format control bits (FC[1–0] in the DPMC) affect the HTXR-DRXR
and DTXM-HRXM data paths only (see Table 6-3, HI32 (PCI Master Data Transfer
Formats, on page 6-8). The target data transfer format control bits (HTF[1–0] and HRF[1–0]
in the HCTR) affect the HTXR–DRXR and DTXS–HRXS data paths only (see Table 6-4,
Transmit Data Transfer Format, on page 6-9 and Table 6-5, Receive Transfer Data Formats,
on page 6-10). The data paths to the other host registers are not affected by the data transfer
format control bits.
6.3.1 Host-to-DSP Data Path
In PCI mode data transfers in which the HI32 is the master (DCTR[HM] = $1) with
DPMC[FC]
≠
$0, the host-to-DSP data path is a 24-bit wide FIFO that is six words deep. The
host data is written into the host side of the FIFO (HTXR) as 24-bit words, and the DSP56300
core reads 24-bit words from the DSP side (DRXR). In PCI mode data transfers in which the
HI32 is the master (DCTR[HM] = $1) with DPMC[FC] = $0, and In PCI mode data
transfers in which the HI32 is the target (DCTR[HM] = $1) with HTF = $0, the
host-to-DSP data path operates 32-bit wide FIFO that is three words deep. The host data is
written into the HTXR as 32-bit words, and the DSP56300 core reads 24-bit words from the
DRXR. Each word read by the DSP56300 core contains 16 bits of data, right aligned and zero
extended. The first word read by the DSP56300 core contains the two least significant bytes
of the 32-bit word read into the HTXR. The second word contains the two most significant
bytes of the 32-bit word read into the HTXR. As the active target, in a memory space write
transaction, the HTXR is accessed if the PCI address is between HI32_base_address: $01C
and HI32_base_address: $FFFC (that is, the host process or views HTXR as a 16377 Dword
write-only memory). As the active master, all data read from the target is written to the
HTXR.