Motorola DSP56301 - Manual (Page 62)

Program Memory Space
3 -2 DSP56301 User’s Manual
3.1.1 Internal Program Memory
The default on-chip program memory consists of a 24-bit-wide, high-speed, SRAM
occupying the lowest 4 K (default), 3 K, 2 K, or 1 K locations in program memory space,
depending on the settings of the OMR[MS] and SR[CE] bits. Section 4.3.2, Operating Mode
Register (OMR), on page 4-12 provides details on the MS bit. Section 4.3.1, Status Register
(SR), on page 4-6 provides details on the CE bit. The default on-chip program RAM is
organized in 16 banks with 256 locations each (4 K). Setting the MS bit switches four banks
of program memory to the X data memory and an additional four banks of program memory
to the Y data memory. Setting the CE bit switches four banks of internal program memory to
the Instruction Cache and reassigns its address to external program memory. The internal
memory addresses for the Instruction Cache vary depending on the setting of the MS and CE
bits. Refer to the memory maps in Section 3.7 for detailed information about the program
memory configurations.
3.1.2 Memory Switch Modes—Program Memory
Memory switch mode allows reallocation of portions of program RAM to X and Y data
RAM. OMR[7] is the memory switch (MS) bit that controls this function, as follows:
n When the MS bit is cleared, program memory consists of the default 4 K
×
24-bit
memory space described in the previous section. In this default mode, the lowest
external program memory location is $1000. If the CE bit is set, the program memory
consists of the lowest 3 K
×
24-bits of memory space and the lowest external program
memory location is $0C00.
n When the MS bit is set, the highest 2 K
×
24-bit portion of the internal program
memory is switched to internal X and Y data memory. In this mode, the lowest
external program memory location is $800. If the CE bit is set and the MS bit is set, the
program memory consists of the lowest 1 K
×
24-bits of memory space and the lowest
external program memory location is $400.
3.1.3 Instruction Cache
In program memory space, the location of the internal Instruction Cache (when enabled by the
CE bit) varies depending on the setting of the MS bit, as noted above. Refer to the memory
maps in Section 3.7 for detailed address information. When the instruction cache is enabled
(that is, the SR[CE] bit is set), 1 K program words switch to instruction cache and are not
accessible via addressing; the address range switches to external program memory.