Motorola DSP56301 - Manual (Page 7)

Contents vii
4.9 JTAG Identification (ID) Register ....................................................................................... 4-35
4.10 JTAG Boundary Scan Register (BSR)................................................................................. 4-35
Chapter
5
Programming the Peripherals
5.1 Peripheral Initialization Steps ................................................................................................ 5-1
5.2 Mapping the Control Registers .............................................................................................. 5-2
5.3 Data Transfer Methods .......................................................................................................... 5-2
5.3.1 Polling .................................................................................................................................... 5-2
5.3.2 Interrupts ................................................................................................................................ 5-3
5.3.3 DMA ...................................................................................................................................... 5-4
5.3.4 Advantages and Disadvantages ............................................................................................. 5-4
5.4 General-Purpose Input/Output (GPIO) .................................................................................. 5-4
5.4.1 Port B Signals and Registers.................................................................................................. 5-5
5.4.2 Port C Signals and Registers.................................................................................................. 5-6
5.4.3 Port D Signals and Registers ................................................................................................. 5-6
5.4.4 Port E Signals and Registers .................................................................................................. 5-6
5.4.5 Triple Timer Signals and Registers ....................................................................................... 5-7
Chapter
6
Host Interface (HI32)
6.1 Features .................................................................................................................................. 6-1
6.2 Overview................................................................................................................................ 6-4
6.3 Data Transfer Paths................................................................................................................ 6-6
6.3.1 Host-to-DSP Data Path .......................................................................................................... 6-6
6.3.2 DSP-To-Host Data Path......................................................................................................... 6-7
6.4 Reset States .......................................................................................................................... 6-12
6.5 DSP-Side Operating Modes................................................................................................. 6-12
6.5.1 Terminate and Reset (DCTR[HM] = $0)........................................................................... 6-13
6.5.2 PCI Mode (DCTR[HM] = $1) ........................................................................................... 6-13
6.5.3 Universal (DCTR[HM] = $2) and Enhanced Universal (DCTR[HM] = $3) Bus Modes 6-15
6.5.4 GPIO Mode (DCTR[HM] = $4) ........................................................................................ 6-16
6.5.5 Self-Configuration Mode (DCTR[HM] = $5) ................................................................... 6-16
6.6 Host Port Pins ...................................................................................................................... 6-18
6.7 HI32 DSP-Side Programming Model .................................................................................. 6-22
6.7.1 DSP Control Register (DCTR) ............................................................................................ 6-23
6.7.2 DSP PCI Control Register (DPCR) ..................................................................................... 6-26
6.7.3 DSP PCI Master Control Register (DPMC) ........................................................................ 6-30
6.7.4 DSP PCI Address Register (DPAR) .................................................................................... 6-33
6.7.5 DSP Status Register (DSR).................................................................................................. 6-35
6.7.6 DSP PCI Status Register (DPSR) ........................................................................................ 6-38
6.7.7 DSP Receive Data FIFO (DRXR) ....................................................................................... 6-41
6.7.8 DSP Master Transmit Data Register (DTXM) .................................................................... 6-42
6.7.9 DSP Slave Transmit Data Register (DTXS)........................................................................ 6-42