Motorola DSP56301 - Manual (Page 132)

DSP-Side Operating Modes
6 -14 DSP56301 User’s Manual
Example 6-1. PCI /DMA Throughput (32-Bit)
PCI clock = 33 MHz
56301 core clock = 66 MHz
33-bit PCI mode
1 wait state SRAM
DMA transfers: SRAM -> host transmit FIFO (master or slave)
Best throughput rate is 14.14 Mwords/sec. Here’s why...
1: HI32 max transfer rate (32-bit)
(pci_cyc + pci_w.s) x multfactor = tot_cyc
1 + 1.33 x 2 = 4.67
multfactor = 2 because f_core = 66 MHz and f_pci = 33 MHz.
Since 4 2/3 (HI32) > 2 (core), this dominates, so the answer is
66/4.67 = 14.14 Mwords/s.
2: (DMA transfer internal memory)
DRXR --> (DMA) --> internal X:
2( 1 (src) + 1 (dest) + 0 (w.s.) ) = 2 * 2 = 4 (DMA faster than HI32)
= > 66 / 4.67 = 14.14 Mwords/sec (HI32-constrained)
3: (dma transfer external memory)
core cycles (DMA)
-----------------
1 DMA source access
1 external wait state
1 DMA destination access
--
3 total
DRXR --> (DMA) --> external X:
2( 1 (src) + 1 (dest) + 1 (w.s.) ) = 2 * 3 = 6 (DMA slower than HI32)
= > 66 / 6 = 11 Mwords/sec (DMA-constrained)
Example 6-2. PCI /DMA Throughput (24-Bit)
PCI clock = 33 MHz
56301 core clock = 66 MHz
24-bit PCI mode
1 wait state SRAM
DMA transfers: SRAM -> host transmit FIFO (master or slave)
Best throughput rate is 33 Mwords/sec. Here’s why...
1: HI32 max transfer rate (24 bit)