Motorola DSP56301 - Manual (Page 49)

Host Interface (HI32)
Signals/Connections 2 -19
HP27 HREQ
Bus Request
Tri-state, Output pin.
Indicates to the arbiter that the HI32
requires use of the bus.
HREQ is deasserted in the same PCI
clock that the HI32 asserts HFRAME.
As during the STOP reset HREQ is
high impedance; an external pull-up
should be connected if it is connected
to the PCI bus arbiter. HTA
Host Transfer Acknowledge
Tri-state, Output pin.
For high speed data transfer between the
HI32 and an external host when the host uses
a non-interrupt driven handshake mechanism.
If the HI32 deasserts HTA at the beginning of
the host access, the host should extend the
access as long as HTA is deasserted. The
polarity of the HTA pin is controlled by HTAP
in the DCTR.
The HTA pin is asserted if:
n
during a data read valid data is present
on HD23-HD0 (HRRQ=1 in the HSTR).
n
during a data write it indicates the HI32
is ready to accept data (HTRQ=1 in the
HSTR).
n
during a vector write it indicates the
HI32 is ready to accept a new host
command (HC=0 in the HCVR).
disconnected
HP28 HSERR
Host System Error
Open drain output pin
1
.
Reports address parity errors and
other errors where the result will be
catastrophic. Asserted for a single
PCI clock by the HI32.
HIRQ
Host Interrupt Request
Output pin
1
.
Used by the HI32 to request service from the
host processor. HIRQ may be connected to
an interrupt request pin of a host processor, a
transfer request of a DMA controller or a
control input of external circuitry.
HIRQ is initially asserted by the HI32 when an
interrupt request is enabled (TREQ=1 or
RREQ=1) and the corresponding data path is
ready for a data transfer.
If the HIRH bit in the DCTR is cleared: HIRQ
assertion is a pulse with a width controlled by
the CLAT register.
If HIRH is set: HIRQ is deasserted at the
beginning of a corresponding host data
access (read or write), or masked (by
TREQ=0 or RREQ=0) or disabled (DMAE=1).
HIRQ is asserted again after the host access
(regardless of the HIRH value), if enabled and
the corresponding data path is ready for a
data transfer. The HIRQ drive (driven or open
drain) is controlled by the HIRD bit in the
DCTR.
disconnected
Table 2-12. Host Port Pins (HI32) (Continued)
Signal
Name
PCI
Universal Bus Mode
Enhanced Universal Bus Mode GPIO