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Motorola DSP56301 User Manual

Page 54

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Enhanced Synchronous Serial Interface 0

2

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DSP56301 User’s Manual

SCK0

PC3

Input/
Output

Input or Output

Input

Serial Clock—Provides the serial bit rate clock for the ESSI.
The SCK0 is a clock input or output, used by both the
transmitter and receiver in synchronous modes or by the
transmitter in asynchronous modes.

Although an external serial clock can be independent of and
asynchronous to the DSP system clock, it must exceed the
minimum clock cycle time of 6T (that is, the system clock
frequency must be at least three times the external ESSI
clock frequency). The ESSI needs at least three DSP phases
inside each half of the serial clock.

Port C 3—The default configuration following reset is GPIO
input PC3. When configured as PC3, signal direction is
controlled through PRR0. The signal can be configured as an
ESSI signal SCK0 through PCR0.

This signal has a weak keeper to maintain the last state even
if all drivers are tri-stated.

SRD0

PC4

Input/
Output

Input or Output

Input

Serial Receive Data—Receives serial data and transfers the
data to the ESSI receive shift register. SRD0 is an input when
data is being received.

Port C 4—The default configuration following reset is GPIO
input PC4. When configured as PC4, signal direction is
controlled through PRR0. The signal can be configured as an
ESSI signal SRD0 through PCR0.

This signal has a weak keeper to maintain the last state even
if all drivers are tri-stated.

STD0

PC5

Input/
Output

Input or Output

Input

Serial Transmit Data—Transmits data from the serial
transmit shift register. STD0 is an output when data is
transmitted.

Port C 5—The default configuration following reset is GPIO
input PC5. When configured as PC5, signal direction is
controlled through PRR0. The signal can be configured as an
ESSI signal STD0 through PCR0.

This signal has a weak keeper to maintain the last state even
if all drivers are tri-stated.

Table 2-13. Enhanced Synchronous Serial Interface 0 (Continued)

Signal Name

Type

State During

Reset

Signal Description