Motorola DSP56301 - Manual (Page 228)

ESSI Programming Model
7 -30 DSP56301 User’s Manual
7.5.5 ESSI Receive Data Register (RX)
The Receive Data Register (RX) is a 24-bit read-only register that accepts data from the
receive shift register as it becomes full, according to Figure 7-12 and Figure 7-13. The data
read is aligned according to the value of the ALC bit. When the ALC bit is cleared, the MSB
is bit 23, and the least significant byte is unused. When the ALC bit is set, the MSB is bit 15,
and the most significant byte is unused. Unused bits are read as 0. If the associated interrupt is
enabled, the DSP is interrupted whenever the RX register becomes full.
7.5.6 ESSI Transmit Shift Registers
The three 24-bit transmit shift registers contain the data being transmitted, as in Figure 7-12
and Figure 7-13. Data is shifted out to the serial transmit data signals by the selected (whether
internal or external) bit clock when the associated frame sync I/O is asserted. The word-length
control bits in CRA determine the number of bits that must be shifted out before the shift
registers are considered empty and can be written again. Depending on the setting of the
CRA, the number of bits to be shifted out can be 8, 12, 16, 24, or 32. Transmitted data is
aligned according to the value of the ALC bit. When ALC is cleared, the MSB is Bit 23 and
the least significant byte is unused. When ALC is set, the MSB is Bit 15 and the most
significant byte is unused. Unused bits are read as 0. Data shifts out of these registers MSB
first if the SHFD bit is cleared and LSB first if SHFD is set.