Motorola DSP56301 - Manual (Page 168)

Host-Side Programming Model
6 -50 DSP56301 User’s Manual
13 0 Reserved. Write to zero for future compatibility.
12–11 HRF[1–0] 0 UBM
PCI
Host Receive Data Transfer Format
Define data transfer formats for DSP-to-host communication. The data
transfer format converter (HDTFC) operates according to the specified
HRF[1–0] (See Table 6-5,
Receive Transfer Data Formats, on
page 6-10). The personal hardware reset clears HRF[1–0].
DSP-to-PCI host data transfer formats (DCTR[HM] = $1):
n
If HCTR[HRF] = $0 (32-bit data mode):
The two least significant bytes of two words written to the DTXS
are transferred to the HRXS. The two least significant bytes of the
first word written to the DTXS are transferred to the two least
significant bytes of the HRXS. The two least significant bytes of the
second word written to the DTXS are transferred to the two most
significant bytes of the HRXS. All four HRXS bytes are output to
the HAD[31–0] pins.
n
If HCTR[HRF] = $1:
The data written to the DTXS is transferred to the three least
significant HRXS bytes and output to the HAD[31–0] pins as right
aligned and zero extended in the most significant byte.
n
If HCTR[HRF] = $2:
The data written to the DTXS is transferred to the three least
significant HRXS bytes and output to the HAD[31–0] pins as left
aligned and zero filled in the least significant byte.
n
If HCTR[HRF] = $3:
The data written to the DTXS is transferred to the three least
significant HRXS bytes and output to the HAD[31–0] pins as right
aligned and sign extended in the most significant byte.
Universal Bus mode DSP-to-host data transfer formats (DCTR[HM] = $2
or $3):
n
If HCTR[HRF] = $0:
The data written to the DTXS is transferred to the HRXS and
output to the HI32 data pins HD[23–0].
n
If HCTR[HRF] = $1 or $2:
The two least significant bytes of the data written to the DTXS is
transferred to the HRXS and output to HI32 data pins HD[15–0].
n
If HCTR[HRF] = $3:
The two most significant bytes of the data written to the DTXS is
transferred to the HRXS and output to HI32 data pins HD[15–0].
To assure proper operation, HRF[1–0] can be changed only if the
DSP-to-host slave data path is empty. In addition, switching between
32-bit data modes and non-32-bit data modes can occur only in the
personal software reset state (DCTR[HM] = $0 and DSR[HACT] = 0).
10 0 Reserved. Write to zero for future compatibility.
Table 6-22. Host Interface Control Register (HCTR) Bit Definitions (Continued)
Bit
Number
Bit Name
Reset
Value
Mode Description