Motorola DSP56301 - Manual (Page 295)

Triple Timer Module Programming Model
Triple Timer Module 9 -33
9.4.5 Timer Load Register (TLR)
The TLR is a 24-bit write-only register. In all modes, the counter is preloaded with the TLR
value after the TCSR[TE] bit is set and a first event occurs.
n In timer modes, if the TCSR[TRM] bit is set, the counter is reloaded each time after it
reaches the value contained by the timer compare register and the new event occurs.
n In measurement modes, if TCSR[TRM] and TCSR[TE] are set, the counter is reloaded
with the value in the TLR on each appropriate edge of the input signal.
n In PWM modes, if TCSR[TRM] is set, the counter is reloaded each time after it
overflows and the new event occurs.
n In watchdog modes, if TCSR[TRM] is set, the counter is reloaded each time after it
reaches the value contained by the timer compare register and the new event occurs. In
this mode, the counter is also reloaded whenever the TLR is written with a new value
while TCSR[TE] is set.
n In all modes, if TCSR[TRM] is cleared (TRM = 0), the counter operates as a
free-running counter.
4 Width of the high input
pulse is measured. Width of the low input
pulse is measured.
— —
5 Period is measured between
the rising edges of the input
signal. Period is measured
between the falling edges
of the input signal.
— —
6 Event is captured on the
rising edge of the signal
from the TIO signal. Event is captured on the
falling edge of the signal
from the TIO signal.
— —
7
— —
Pulse generated by
the timer has
positive polarity. Pulse generated by the
timer has negative
polarity.
9
— —
Pulse generated by
the timer has
positive polarity. Pulse generated by the
timer has negative
polarity.
10
— —
Pulse generated by
the timer has
positive polarity. Pulse generated by the
timer has negative
polarity.
Table 9-4. Inverter (INV) Bit Operation (Continued)
Mode
TIO Programmed as Input TIO Programmed as Output
INV = 0 INV = 1 INV = 0 INV = 1