Motorola DSP56301 - Manual (Page 8)

viii DSP56303 DSP56301 User’s Manual
6.7.10 DSP Host Port GPIO Direction Register (DIRH)................................................................ 6-43
6.7.11 DSP Host Port GPIO Data Register (DATH) ...................................................................... 6-43
6.8
Host-Side Programming Model ........................................................................................... 6-44
6.8.1 HI32 Control Register (HCTR) ........................................................................................... 6-48
6.8.2 Host Interface Status Register (HSTR)................................................................................ 6-56
6.8.3 Host Command Vector Register (HCVR) ........................................................................... 6-59
6.8.4 Host Master Receive Data Register (HRXM) ..................................................................... 6-61
6.8.5 Host Slave Receive Data Register (HRXS) ......................................................................... 6-61
6.8.6 Host Transmit Data Register (HTXR) ................................................................................. 6-62
6.8.6.1 PCI Mode (DCTR[HM] = $1) ....................................................................................... 6-63
6.8.6.2 Universal Bus mode (DCTR[HM] = $2 or $3).............................................................. 6-63
6.8.7 Device ID/Vendor ID Configuration Register (CDID/CVID)............................................. 6-64
6.8.8 Status/Command Configuration Register (CSTR/CCMR).................................................. 6-64
6.8.9 Class Code/Revision ID Configuration Register (CCCR/CRID) ........................................ 6-67
6.8.10 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS) ..................... 6-68
6.8.11 Memory Space Base Address Configuration Register (CBMA) ......................................... 6-70
6.8.12 Subsystem ID and Subsystem Vendor ID Configuration Register (CSID) ......................... 6-71
6.8.13 Interrupt Line-Interrupt Pin Configuration Register(CILP) ................................................ 6-73
6.9
HI32 Programming Model/Quick Reference....................................................................... 6-74
Chapter
7
Enhanced Synchronous Serial Interface (ESSI)
7.1 ESSI Enhancements ............................................................................................................... 7-2
7.2 ESSI Data and Control Signals .............................................................................................. 7-3
7.2.1 Serial Transmit Data Signal (STD)........................................................................................ 7-3
7.2.2 Serial Receive Data Signal (SRD) ......................................................................................... 7-3
7.2.3 Serial Clock (SCK) ................................................................................................................ 7-3
7.2.4 Serial Control Signal (SC0) ................................................................................................... 7-4
7.2.5 Serial Control Signal (SC1) ................................................................................................... 7-4
7.2.6 Serial Control Signal (SC2) ................................................................................................... 7-6
7.3 Operation ............................................................................................................................... 7-6
7.3.1 ESSI After Reset .................................................................................................................... 7-6
7.3.2 Initialization ........................................................................................................................... 7-6
7.3.3 Exceptions.............................................................................................................................. 7-7
7.4 Operating Modes: Normal, Network, and On-Demand....................................................... 7-10
7.4.1 Normal/Network/On-Demand Mode Selection ................................................................... 7-10
7.4.2 Synchronous/Asynchronous Operating Modes ................................................................... 7-11
7.4.3 Frame Sync Selection .......................................................................................................... 7-11
7.4.4 Frame Sync Signal Format .................................................................................................. 7-11
7.4.5 Frame Sync Length for Multiple Devices............................................................................ 7-12
7.4.6 Word Length Frame Sync and Data Word Timing.............................................................. 7-12
7.4.7 Frame Sync Polarity............................................................................................................. 7-12
7.4.8 Byte Format (LSB/MSB) for the Transmitter...................................................................... 7-13
7.4.9 Flags..................................................................................................................................... 7-13
7.5 ESSI Programming Model................................................................................................... 7-14