Motorola DSP56301 User Manual
Page 360
Index
-4
DSP56301 User’s Manual
PCI Host Data Transfer Complete (HDTC) 6-39
PCI Master Abort (MAB) 6-40
PCI Master Address Request (MARQ) 6-40
PCI Master Receive Data Request (MRRQ) 6-41
PCI Master Transmit Data Request (MTRQ) 6-41
PCI Master Wait States (MWS) 6-41
PCI Target Abort (TAB) 6-40
PCI Target Disconnect (TDIS) 6-40
PCI Target Retry (TRTY) 6-39
PCI Time Out Termination (TO) 6-39
Remaining Data Count (RDC[5–0]) 6-38
Remaining Data Count Qualifier (RDCQ) 6-38
DSP PCI Transaction Address (High) (AR[31–16])
bits 6-32
DSP PCI Transaction Address (Low) (AR[15–0])
bits 6-34
DSP Receive Data FIFO (DRXR) 6-41
DSP Slave Transmit Data Register (DTXS) 6-7
DSP Status Register (DSR)
HI32 Active (HACT) 6-35
Host Command Pending (HCP) 6-37
Host Flags 2–0 (HF[2–0]) 6-36
Slave Receive Data Request (SRRQ) 6-36
Slave Transmit Data Request (STRQ) 6-37
DSP56000
code compatibility 1-4
DSP56300
code compatibility 1-4
core 1-1
Family Manual 1-1
DSP56301
Technical Data 1-1
DSP56301 Operating Modes 4-2
dynamic memory configuration switching 3-5
E
Enhanced Synchronous Serial Interface (ESSI) 1-5
,
,
24-bit fractional data 7-16
after reset 7-6
Asynchronous mode 7-4
audio enhancements 7-2
byte format 7-13
clock generator 7-11
Clock Sources 7-3
codec 7-13
control and time slot registers 7-6
control direction of SC2 I/O signal 7-23
Control Register A (CRA)
Alignment Control (ALC) 7-16
Frame Rate Divider Control (DC) 7-16
Prescale Modulus Select (PM) 7-16
Prescaler Range (PSR) 7-16
programming sheet B-32
Select SCK (SSC1) 7-15
Word Length Control (WL) 7-15
Control Register B (CRB)
Clock Polarity (CKP) 7-22
Clock Source Directions (SCKD) 7-22
Frame Sync Length (FSL) 7-22
Frame Sync Polarity (FSP) 7-22
Frame Sync Relative Timing (FSR) 7-22
Mode Select (MOD) 7-21
programming sheet B-33
Receive Enable (RE) 7-20
Receive Exception Interrupt Enable (REIE) 7-19
Receive Interrupt Enable (RIE) 7-19
Receive Last Slot Interrupt Enable 7-19
Serial Control Direction 0 (SCD0) 7-23
Serial Control Direction 1 (SCD1) 7-23
Serial Control Direction 2 (SCD2) 7-23
Serial Output Flag 0 (OF0) 7-23
Serial Output Flag 1 (OF1) 7-23
Shift Direction (SHFD) 7-22
Synchronous/Asynchronous (SYN) 7-21
Transmit 0 Enable (TE0) 7-20
Transmit 1 Enable (TE1) 7-21
Transmit 2 Enable (TE2) 7-21
Transmit Exception Interrupt Enable
(TEIE) 7-19
Transmit Interrupt Enable (TIE) 7-20
Transmit Last Slot Interrupt Enable (TLIE) 7-19
control registers 7-14
data and control signals 7-3
DMA 7-7
exception configuration 7-9
exceptions 7-7
receive last slot interrupt 7-8
transmit data 7-8
transmit data with exception status 7-8
transmit last slot interrupt 7-8
flags 7-13
frame rate divider 7-10
frame sync
generator 7-17
length 7-12
polarity 7-12
selection 7-11
signal 7-7
word length 7-12
initialization 7-6
initialization example 7-7
internally generated clock and frame sync 7-7
interrupt 7-7
Interrupt Service Routine (ISR) 7-9
interrupt trigger event 7-9
multiple serial device selection 7-4