Motorola DSP56301 - Manual (Page 24)

DSP56300 Core Functional Blocks
1 -8 DSP56301 User’s Manual
arithmetic used in the address register update calculation. The modifier value is decoded in
the address ALU.
1.4.3 Program Control Unit (PCU)
The PCU prefetches and decodes instructions, controls hardware DO loops, and processes
exceptions. Its seven-stage pipeline controls the different processing states of the DSP56300
core. The PCU consists of three hardware blocks:
n Program decode controller — decodes the 24-bit instruction loaded into the instruction
latch and generates all signals necessary for pipeline control.
n Program address generator — contains all the hardware needed for program address
generation, system stack, and loop control.
n Program interrupt controller — arbitrates among all interrupt requests (internal
interrupts, as well as the five external requests
IRQA , IRQB , IRQC , IRQD , and NMI ), and
generates the appropriate interrupt vector address.
PCU features include the following:
n Position-independent code support
n Addressing modes optimized for DSP applications (including immediate offsets)
n On-chip instruction cache controller
n On-chip memory-expandable hardware stack
n Nested hardware DO loops
n Fast auto-return interrupts
n Hardware system stack
The PCU uses the following registers:
n Program counter register
n Status register
n Loop address register
n Loop counter register
n Vector base address register
n Size register
n Stack pointer
n Operating mode register
n Stack counter register