Motorola DSP56301 - Manual (Page 259)

SCI Programming Model
Serial Communication Interface (SCI) 8 -23
the data bus are read as zeros. Similarly, when SRXM is read, the contents of SRX are placed
into the middle byte of the bus, and when SRXH is read, the contents of SRX are placed into
the high byte with the remaining bits are read as 0s. This way of mapping SRX efficiently
packs three bytes into one 24-bit word by ORing three data bytes read from the three
addresses.
The SCR WDS0, WDS1, and WDS2 control bits define the length and format of the serial
word. The SCR receive clock mode (RCM) defines the clock source.
In Synchronous mode, the start bit, the eight data bits, the address/data indicator bit or the
parity bit, and the stop bit are received, respectively. Data bits are sent LSB first if SSFTD is
cleared, and MSB first if SSFTD is set. In Synchronous mode, a gated clock provides
synchronization. In either Synchronous or Asynchronous mode, when a complete word is
clocked in, the contents of the shift register can be transferred to the SRX and the flags;
RDRF, FE, PE, and OR are changed appropriately. Because the operation of the receive shift
register is transparent to the DSP, the contents of this register are not directly accessible to the
programmer.
8.6.4.2 SCI Transmit Register (STX)
The transmit data register is a one-byte-wide register mapped into four addresses as STXL,
STXM, STXH, and STXA. In Asynchronous mode, when data is to be transmitted, STXL,
STXM, and STXH are used. When STXL is written, the low byte on the data bus is
transferred to the STX. When STXM is written, the middle byte is transferred to the STX.
When STXH is written, the high byte is transferred to the STX. This structure makes it easy
for the programmer to unpack the bytes in a 24-bit word for transmission. TDXA should be
written in 11-bit asynchronous multidrop mode when the data is an address and the
programmer wants to set the ninth bit (the address bit). When STXA is written, the data from
the low byte on the data bus is stored in it. The address data bit is cleared in 11-bit
asynchronous multidrop mode when any of STXL, STXM, or STXH is written. When either
STX (STXL, STXM, or STXH) or STXA is written, TDRE is cleared.
The transfer from either STX or STXA to the transmit shift register occurs automatically, but
not immediately, after the last bit from the previous word is shifted out; that is, the transmit
shift register is empty. Like the receiver, the transmitter is double-buffered. However, a delay
of two to four serial clock cycles occurs between when the data is transferred from either STX
or STXA to the transmit shift register and when the first bit appears on the
TXD signal. (A
serial clock cycle is the time required to transmit one data bit.)
The transmit shift register is not directly addressable, and there is no dedicated flag for this
register. Because of this fact and the two- to four-cycle delay, two bytes cannot be written
consecutively to STX or STXA without polling, because the second byte might overwrite the
first byte. Thus, you should always poll the TDRE flag prior to writing STX or STXA to