Motorola DSP56301 - Manual (Page 134)

DSP-Side Operating Modes
6 -16 DSP56301 User’s Manual
In addition, for Universal Bus mode, pins HP[22–20] are GPI/O. For Enhanced Universal Bus
mode, two control signals (data direction and data output enable) are output to an optional
external data buffer. Also, there is host select acknowledge output.
6.5.4 GPIO Mode (DCTR[HM] = $4)
n General-purpose I/O (GPIO) port, pins HP[23–0].
n Pins HP[48–33], HP[30–24] are disconnected.
n HP31 and HP32 are unused and must be forced or pulled up to V
CC
.
n Minimum current consumption.
6.5.5 Self-Configuration Mode (DCTR[HM] = $5)
n Indirect write-only DSP56300 core access to to all registers in the PCI configuration
space except CDID/CVID.
n All host port pins are in the disconnected state.
In Self-Configuration mode, the HI32 base address and HIRQ pulse width are programmed
for operation in the Universal Bus mode, and the configuration registers are prorammed for
operation in a PCI environment without an external system configurator.
In Self-Configuration mode (DCTR[HM] = $5), the DSP56300 core can indirectly write to
all the writeable HI32 configuration registers. The DSP56300 core writes the 32-bit data to
the AR bits of the DPMC and DPAR registers (the remaining bits in these registers are
ignored). The two most significant bytes of the 32 bits are written to the DPMC, the two least
significant, to the DPAR. Therefore, the 16 most significant bits of the 32 bit PCI data word
reside in the DPMC AR bits (16 least significant bits of DPMC). The 16 least significant bits
of the 32-bit PCI data word reside in the DPAR AR bits (16 least significant bits of DPAR).
The HI32 hardware transfers the data to the configuration register. The registers must be
written sequentially beginning with the CSTR/CCMR register (location $04). After each
write to the DPAR, a 32-bit data word (Dword) is transferred to the accessed register, and an
internal pointer advances to point to the next Dword location in the configuration space.
Note: At least one DSP instruction must appear between writing the Self-Configuration
mode (HM[2–0] = $5) and the first write to the DPAR if the first write requires
one DSP clock cycle (for example, move immediate and move from external
memory require more than one clock cycle).
If the SIDR/SVID register is to be written in Self-Configuration mode and the host has
already written the CBMA address, this address is over written by this prodcedure. You must
be careful to ensure that this does not happen. In the example code that follows, the DPMC
AR bits are loaded with the Base Address upper 16 bits of the 32 bit PCI word (Dword) and