Motorola DSP56301 - Manual (Page 209)

Operating Modes: Normal, Network, and On-Demand
Enhanced Synchronous Serial Interface (ESSI) 7 -11
7.4.2 Synchronous/Asynchronous Operating Modes
The transmit and receive sections of the ESSI interface are synchronous or asynchronous. The
transmitter and receiver use common clock and synchronization signals in Synchronous
mode; they use separate clock and sync signals in Asynchronous mode. The CRB[SYN] bit
selects synchronous or asynchronous operation. When the SYN bit is cleared, the ESSI TX
and RX clocks and frame sync sources are independent. If the SYN bit is set, the ESSI TX
and RX clocks and frame sync are driven by the same source (either external or internal).
Since the ESSI operates either synchronously or asynchronously, separate receive and
transmit interrupts are provided.
Transmitter 1 and transmitter 2 operate only in Synchronous mode. Data clock and frame
sync signals are generated internally by the DSP or obtained from external sources. If clocks
are internally generated, the ESSI clock generator derives bit clock and frame sync signals
from the DSP internal system clock. The ESSI clock generator consists of a selectable fixed
prescaler with a programmable prescaler for bit rate clock generation and a programmable
frame-rate divider with a word-length divider for frame-rate sync-signal generation.
7.4.3 Frame Sync Selection
The transmitter and receiver can operate independently. The transmitter can have either a
bit-long or word-long frame-sync signal format, and the receiver can have the same or another
format. The selection is made by programming the CRB FSL[1–0], FSR, and FSP bits.
7.4.4 Frame Sync Signal Format
CRB[FSL1] controls the frame sync signal format.
n If CRB[FSL1] is cleared, the receive frame sync is asserted during the entire data
transfer period. This frame sync length is compatible with Motorola codecs, serial
peripherals that conform to the Motorola SPI, serial A/D and D/A converters, shift
registers, and telecommunication pulse code modulation serial I/O.
n If CRB[FSL1] is set, the receive frame sync pulses active for one bit clock
immediately before the data transfer period. This frame sync length is compatible with
Intel and National Semiconductor Corporation components, codecs, and
telecommunication pulse code modulation serial I/O.