Motorola DSP56301 - Manual (Page 125)

Data Transfer Paths
Host Interface (HI32) 6 -7
In PCI mode data transfers in which the HI32 is the target (DCTR[HM] = $1) with
HCTR[HTF]
≠
$0, the host-to-DSP data path is a six word deep, 24-bit wide FIFO. The host
writes 24-bit words to the HTXR, and the DSP56300 core reads 24-bit words from the
DRXR. In Universal Bus mode data transfers, the host-to-DSP data path is a five word deep,
24-bit wide FIFO. The host writes 24-bit words to the HTXR, and the DSP56300 core reads
24-bit words from the DRXR.
Note: To guarantee proper HI32 operation, the DMA should service the HI32 under the
following restrictions:
— Two DMA channels should not service the DRXR FIFO if master and slave data
is mixed there.
— The DMA data transfers should not be concurrent with the DSP56300 core data
transfers to/from the same HI32 data FIFO.
6.3.2 DSP-To-Host Data Path
In PCI mode data transfers in which the HI32 is the master (DCTR[HM] = $1) with
DPMC[FC]
≠
$0, the master DSP-to-host data path (DTXM-HRXM) is an eight word deep
FIFO. The DSP56300 core writes to the DSP side of the FIFO (DTXM). The data is output to
the bus from the host side (HRXM). In PCI mode data transfers in which the HI32 is the
master (DCTR[HM] = $1) with DPMC[FC] = $0, the master DSP-to-host data path is a
FIFO four words deep and 32 bits wide. The DSP56300 core writes 24-bit words to the
DTXM. Each word written by the DSP56300 core contains 16-bits of significant data, right
aligned, the most significant byte is not transmitted. The first word written by the DSP56300
core contains the two least significant bytes of the 32-bit word to be output from the HRXM.
The second word written by the DSP56300 core contains the two most significant bytes of the
32-bit word output from the HRXM. Each time a 32-bit word is output from the HRXM, the
32-bits of significant data located in two words written to the DTXM are output.
In PCI mode data transfers in which the HI32 is the target (DCTR[HM] = $1) with
HCTR[HRF]
≠
$0 and in Universal Bus mode data transfers, the slave DSP-to-host data path
(DTXS-HRXS) is a six word deep FIFO. The DSP56300 core writes 24-bit words to the
DTXS. The data is output, a word at a time, to the bus from the HRXS.
In PCI mode data transfers in which the HI32 is the target (DCTR[HM] = $1) with
HCTR[HRF] = $0, the slave DSP-to-host data path is a three word deep, 32-bit wide FIFO.
The DSP56300 core writes 24-bit words to the DTXS. Each word written by the DSP56300
core contains 16-bits of significant data, right aligned, the most significant byte is not
transmitted. The first word written by the DSP56300 core contains the two least significant
bytes of the 32-bit word to be output from the HRXS. The second word written by the
DSP56300 core contains the two most significant bytes of the 32-bit word output from the