FUJITSU F2MCTM-16LX - Manual (Page 94)

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CHAPTER 3 INTERRUPTS
3.7.2 EI
2
OS Status Register (ISCS)
This eight-bit register indicates the update direction (increment/decrement), transfer
data format (byte/word), and transfer direction of the buffer address pointer and the I/O
register address pointer. This register also indicates whether the buffer address pointer
or I/O register address pointer is updated or fixed.
■ EI
2
OS Status Register (ISCS)
Figure 3.7-5 is a diagram of the ISCS configuration.
Be sure to write "0" in bit 7 to bit 5 of ISCS.
Figure 3.7-5 ISCS Configuration
Each bit is described below.
[bit 4] IF: Specify whether the I/O register address pointer is updated or fixed.
0: The I/O register address pointer is updated after data transfer.
1: The I/O register address pointer is not updated after data transfer.
Note:
Only increment is allowed.
[bit 3] BW: Specify the transfer data length.
0: Byte
1: Word
[bit 2] BF: Specify whether the buffer address pointer is updated or fixed.
0: The buffer address pointer is updated after data transfer.
1: The buffer address pointer is not updated after data transfer.
Note:
Only the low-order 16 bits of the buffer address pointer are updated. Only increment is allowed.
[bit 1] DIR: Specify the data transfer direction.
0: I/O --> Buffer
1: Buffer --> I/O
[bit 0] SE: Control the termination of the extended intelligent I/O service based on internal
resource requests.
0: The extended intelligent I/O service is not terminated by a internal resource request.
1: The extended intelligent I/O service is terminated by a internal resource request.
7 6 5 4 3 2 1 0
ISCS
(Undefined
when reset)
Reserved Reserved Reserved IF BW BF DIR SE