FUJITSU F2MCTM-16LX - Manual (Page 389)

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CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET
■ CPU Operating Detection Reset Circuit
CPU operating detection reset circuit is a counter for preventing the program out of control. After power-on
reset, it starts automatically. After it starts, it is necessary to keep clearing regularly within the fixed time.
Internal reset is generated when not cleared during the fixed time by an program infinite loop, etc. The
width of internal reset generated by CPU operating detection circuit is five machine cycles.
Figure 19.1-2 Interval Time of CPU operating Detection Reset Circuit
In the mode that CPU stops operating, the circuit stops.
The counter condition of CPU operating detection reset circuit is indicated as follows.
1) Writing "0" to CL bit of LVRC register
2) Internal reset
3) Oscillation clock stop
4) Transition to sleep mode
5) Transition to timebase timer mode
2 20 /F
C
(approx.262ms) *
Interval time
*: It is the interval time at oscillation clock 4 MHz.