FUJITSU F2MCTM-16LX - Manual (Page 137)

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CHAPTER 7 RESETS
stabilization wait time has elapsed, the reset is executed.
●
External reset
An external reset is generated by the L level input to an external reset pin (RST pin). The minimum
required period of the L level is at least 500 ns. Reset operation is performed after oscillation stabilization
wait time elapses.
Note:
If the reset cause is generated during a write operation, the CPU waits for the reset to be cleared after
completion of the instruction only for reset requests via the RST pin. Therefore, the normal write
operation is completed even though a reset is inputted concurrently. However, note that the following two
points.
Note that a reset may prevent the data transfer requested by a string-processing instruction from being
completed because the reset is accepted before a specified number of counters are transferred.
At external bus access, if the cycle is exceeded a certain period by RDY input, the reset is accepted
forcibly without waiting the completion of instruction. Forcible reset is accepted within 16 machine
cycles.
When returning to the main clock mode by the external reset pin (RST pin) from the stop mode, sub-
clock mode, sub-sleep mode, and watch mode, input L level for at least oscillation time of oscillator* +
100
µs.
*: Oscillation time of oscillator is the time that amplitude reaches 90%. It takes several to dozens of ms
for crystal oscillators, hundreds of
µs to several ms for FAR/ceramic oscillators, and 0 ms for external
clocks.
When returning to the main clock mode by the external reset pin (RST pin) from the timebase timer
mode, input L level for at least 100
µs.
●
Software reset
A software reset is generated an internal reset by writing "0" to the RST bit of the low-power consumption
mode control register (LPMCR). The oscillation stabilization wait time is not required for a software reset.
●
Watchdog reset
A watchdog reset is generated by a watchdog timer overflow that occurs when "0" is not written to the
WTE bit of the watchdog timer control register (WDTC) within a given time after the watchdog timer is
activated. The oscillation stabilization wait time is not required for watchdog reset.
●
Low voltage detection reset
The low voltage detection reset is generated when the low voltage (4.0 V
± 0.3 V) is detected.
The oscillation stabilization wait time is not required for the low voltage detection reset.