FUJITSU F2MCTM-16LX - Manual (Page 595)

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APPENDIX B Instructions
■ Effective Address Field
Table B.2-1 lists the address formats specified by the effective address field.
Table B.2-1 Effective Address Field
Code Representation Address format Default bank
00 R0 RW0 RL0
Register direct: Individual parts
correspond to the byte, word, and long
word types in order from the left.
None
01 R1 RW1 (RL0)
02 R2 RW2 RL1
03 R3 RW3 (RL1)
04 R4 RW4 RL2
05 R5 RW5 (RL2)
06 R6 RW6 RL3
07 R7 RW7 (RL3)
08 @RW0
Register indirect
DTB
09 @RW1 DTB
0A @RW2 ADB
0B @RW3 SPB
0C @RW0+
Register indirect with post increment
DTB
0D @RW1+ DTB
0E @RW2+ ADB
0F @RW3+ SPB
10 @RW0+disp8
Register indirect with 8-bit displacement
DTB
11 @RW1+disp8 DTB
12 @RW2+disp8 ADB
13 @RW3+disp8 SPB
14 @RW4+disp8
Register indirect with 8-bit displacement
DTB
15 @RW5+disp8 DTB
16 @RW6+disp8 ADB
17 @RW7+disp8 SPB
18 @RW0+disp16
Register indirect with 16-bit
displacement
DTB
19 @RW1+disp16 DTB
1A @RW2+disp16 ADB
1B @RW3+disp16 SPB
1C @RW0+RW7 Register indirect with index DTB
1D @RW1+RW7 Register indirect with index DTB
1E @PC+disp16 PC indirect with 16-bit displacement PCB
1F addr16 Direct address DTB