FUJITSU F2MCTM-16LX - Manual (Page 653)

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APPENDIX C Timing Diagrams in Flash Memory Mode
■ Write, Data Polling, Read (WE control)
Figure C-2 Write, Data Polling, Read (WE control)
Note:
• Describes the last 2-bus cycle of 4-bus cycle sequences.
• "Fx" in "FxAAAA" described as address is any of FF.
t CH t
CS
t WP t WHWH1
t WC
CE
OE
t RC
AQ18 to AQ0
DQ7 to DQ0
t GHWL
t
CE
t OE
t WPH
t
DS t DH
DQ7 PD A0 H D OUT D OUT
WE
FxAAAA H PA PA
t OH
t
AS t AH
t DF
PA : Write address
PD : Write data
DQ
7
: Reverse output of write data
D
OUT
: Output of write data
3rd bus cycle Data polling