FUJITSU F2MCTM-16LX - Manual (Page 668)

652
INDEX
Bidirectional Communication
Bidirectional Communication Function .............. 433
Bit Timing
Setting Bit Timing ............................................ 494
Block Diagram
Block Diagram of 16-bit Free-run Timer ............ 213
Block Diagram of 16-bit I/O Timer .................... 211
Block Diagram of 16-bit Reload Timer ............... 240
Block Diagram of 8-/10-bit A/D Converter ......... 341
Block Diagram of 8-/16-bit PPG Timer C ........... 286
Block Diagram of 8-/16-bit PPG Timer D ........... 288
Block Diagram of Address Match Detection Function
.......................................................... 507
Block Diagram of CAN Controller ..................... 445
Block Diagram of Clock Supervisor ................... 111
Block Diagram of Delayed Interrupt Generation
Module ................................................. 85
Block Diagram of DTP/External Interrupt .......... 315
Block Diagram of Evaluation Chip ........................ 9
Block Diagram of Flash/Mask ROM Version ........ 11
Block Diagram of Input Capture ........................ 214
Block Diagram of LIN-UART ........................... 387
Block Diagram of LIN-UART Pins .................... 391
Block Diagram of Low Voltage/CPU Operating
Detection Reset Circuit ........................ 374
Block Diagram of Pull-up Control Register (PUCR)
.......................................................... 174
Block Diagram of ROM Mirroring Function Select
Module ............................................... 526
Block Diagram of the Clock Generation Block ...... 95
Block Diagram of the Entire Flash Memory ........ 531
Block Diagram of the External Reset Pin ............ 125
Block Diagram of the Low-Power Consumption
Control Circuit .................................... 137
Block Diagram of Timebase Timer .................... 182
Block Diagram of Watch Timer ......................... 270
Block Diagram of Watchdog Timer ................... 199
Buffer Address Pointer
Buffer Address Pointer (BAP) ............................. 77
Bus Mode
Memory Space in Each Bus Mode ..................... 165
Bus Operation Stop
Conditions for Canceling Bus Operation Stop
(HALT=0) .......................................... 457
Conditions for Setting Bus Operation Stop (HALT=1)
.......................................................... 457
State during Bus Operation Stop (HALT=1) ....... 457
BVAL
Caution for Disabling Message Buffers By BVAL Bits
.......................................................... 503
BY Timing
RST and RY/BY Timing ................................... 641
RY/BY Timing during Writing/erasing ............... 641
C
CAN Controller
Block Diagram of CAN Controller .................... 445
Canceling Transmission Request from CAN
Controller ........................................... 488
Features of CAN Controller .............................. 444
Reception Flowchart of the CAN Controller ....... 493
Starting Transmission of CAN Controller ........... 488
Transmission Flowchart of CAN Controller ....... 489
CAN Direct
Setting of CAN Direct Mode ............................. 504
CAN Direct Mode Register
CAN Direct Mode Register (CDMR)
(Only MB90V340) .............................. 502
CCR
Condition Code Register (CCR) .......................... 42
CDMR
CAN Direct Mode Register (CDMR)
(Only MB90V340) .............................. 502
CE Control
Write,data Polling,read (CE control) .................. 638
Chip Erase
Chip Erase/sector Erase Command Sequence ..... 639
CKSCR
Configuration of the Clock Selection Register
(CKSCR) ............................................. 98
Clock Frequency
Oscillating Clock Frequency and Serial Clock Input
Frequency .......................................... 556
Clock Generation Block
Block Diagram of the Clock Generation Block ..... 95
Clock Mode
Clock Mode ..................................................... 103
Clock Mode Switching ..................................... 158
Clock Mode Transition ..................................... 103
Internal Clock Mode ........................................ 238
Operation in Internal Clock Mode ..................... 255
Program Example in Internal Clock Mode .......... 263
Setting of Internal Clock Mode ......................... 254
Sub-clock Mode ............................................... 116
Sub-clock Mode Transition Operating When
Sub-clock Has Already Stopped ........... 116
Clock Selection Register
Clock Selection Register and List of Reset Value
........................................................... 97
Clock Supervisor
Block Diagram of Clock Supervisor .................. 111
Overview of Clock Supervisor .......................... 110
Prohibition Setting of CR Oscillation Circuit and
Clock Supervisor ................................ 115
Reoperating Setting of CR Oscillation Circuit and
Clock Supervisor ................................ 115
Reset Check by Clock Supervisor ...................... 117