FUJITSU F2MCTM-16LX - Manual (Page 212)

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CHAPTER 12 WATCHDOG TIMER
12.1 Overview of Watchdog Timer
The watchdog timer is a 2-bit counter that uses the timebase timer or watch timer as a
count clock. If the counter is not cleared within a set interval time, the CPU is reset.
■ Functions of Watchdog Timer
• The watchdog timer is a timer counter that is used to prevent program malfunction. When the watchdog
timer is started, the watchdog timer counter must continue to be cleared within a set interval time. If the
set interval time is reached without clearing the watchdog timer counter, the CPU is reset. This is called
watchdog timer.
• The interval time of the watchdog timer depends on the clock cycle input as a count clock and a
watchdog reset occurs between the minimum and maximum times.
• The clock source output destination is set by the watchdog clock select bit in the watch timer control
register (WTC: WDCS).
• The interval time of the watchdog timer is set by the timebase timer output select bit/watch timer output
select bit in the watchdog timer control register (WDTC: WT1, WT0).
Table 12.1-1 lists the interval times of the watchdog timer.