FUJITSU F2MCTM-16LX - Manual (Page 302)

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CHAPTER 16 8-/16-BIT PPG TIMER
16.2.1 Block Diagram for 8-/16-bit PPG Timer C
The 8-/16-bit PPG timer C consists of the following blocks.
■ Block Diagram of 8-/16-bit PPG Timer C
Figure 16.2-2 Block Diagram of 8-/16-bit PPG Timer C
PPGC
CLK
R
S Q
PEN0 PE0 PIE0 PUF0 - - -
PCS2 PCS0 PCM2 PCM1 PCM0 - PCS1
3
2
REV
High level side data bus
Low level side data bus
PPGC reload
register PPGC operation mode control
register (PPGCC)
Re-
served PRLHC
(High level side)
PRLLC
(Low level
PPGC temporary
buffer C (PRLBHC)
Interrupt
request
output*
Select signal
Operation mode
control signal
Reload register
L/H selector
Count start
value
Reload Clear
Pulse selector
Underflow
PPGD underflow
PPGC underflow
(to PPGD)
PPGC down counter
(PCNTC)
Invert
PPGC
output latch
PPG output control circuit
PPGD
output
Timebase timer output(512/HCLK)
Resource clock (1/
φ
)
Resource clock (2/
φ
)
Resource clock (4/ φ )
Resource clock (8/ φ )
Resource clock (16/ φ )
Count
clock
selector
Select signal
PPGC/D count clock select register (PPGCD)
Pin
- : Undefined
Reserved : Reserved bit
HCLK
: Oscillation clock frequency
φ
: Machine clock frequency
* : The interrupt output of 8-/16- bit PPG timer C is combined to one interrupt by OR circuit with the interrupt
request output of PPG timer D.