FUJITSU F2MCTM-16LX User Manual

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CHAPTER 6 CLOCK SUPERVISOR

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The sub-clock supervisor is operated by setting SSVE(CSVCR:bit2) to 1. Please note the programming
of software to do after 10

µs or more has passed since the CR oscillation circuit was set enable.

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Sub-clock Mode

The main clock supervisor automatically becomes disable at the sub-clock mode. The content of enable bit

MSVE never changes. If the main clock was lost after oscillation stability waiting time of 2

/HCLK

(about 0.51 ms: at external 4 MHz) or before the oscillation stability waiting time ends, the main clock

supervisor is valid after it passes of 2

cycles of the CR oscillation clock (about 41 ms: at CR oscillation

100 kHz) at transition from main clock mode to sub clock mode.

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Sub-clock Mode Transition Operating When Sub-clock Has Already Stopped

The behavior that shifts to the sub-clock mode depends on the state of the SRST bit when the stop of the

sub-clock is detected by the sub-clock supervisor while the device is operating in the main clock mode.

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When SRST is set to 0 (initial state), the reset is not generated at transition to the sub-clock mode. In
this case, the CR oscillation clock is used as a sub-clock at transition to the sub-clock mode.

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When SRST is set to 1, the reset is generated at transition to the sub-clock mode.

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Stop Mode

CR oscillation circuit, the main clock, and the sub-clock supervisor automatically become disable at

transition to the stop mode, when all of these functions are enable. Each enable bit of the clock supervisor

control register is not changed. Therefore, after it is released from the stop mode, each enable/disable state

of CR oscillation circuit and clock supervisor keep the state before they changes to the stop mode.

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The CR oscillation circuit immediately becomes enable after released from the stop mode.

•

If the main clock was lost after oscillation stability waiting time of 2

/HCLK (about 0.51 ms: at

external 4 MHz) or before the oscillation stability waiting time ends, the main clock supervisor is

enabled after it passes of 2

cycles of the CR oscillation clock (about 41 ms: at CR oscillation 100

kHz).

•

After it passes of 2

cycles of the CR oscillation clock (For about 2.6 s:CR oscillation 100 kHz), the

sub-clock supervisor is valid.

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Sub-clock Mode with External Single Clock Product

In the sub-clock mode with external single clock product ("S" suffix product), the CR oscillation clock can

be used as a sub-clock.

To use this function, SCKS (bit7 of CSVCR) is set to 1 and SRST is set to 0 (initial value). This function

can not be used with the external dual clock products (no "S" suffix product).