FUJITSU F2MCTM-16LX - Manual (Page 671)

655
INDEX
Correspondence between 16-bit Reload Timer
Interrupt and EI
2
OS ............................. 251
Correspondence between Timebase Timer Interrupt
and EI
2
OS .......................................... 187
Correspondence to EI
2
OS Function ................... 228
EI
2
OS Function of 16-bit Reload Timer ............. 251
EI
2
OS Function of 8-/10-bit A/D Converter ........ 358
EI
2
OS Operation Flow ........................................ 79
Extended Intelligent I/O Service (EI
2
OS) ....... 57, 74
LIN-UART Interrupts and EI
2
OS ...................... 408
EI
2
OS Status Register
EI
2
OS Status Register (ISCS) .............................. 78
EIRR
DTP/External Interrupt Factor Register (EIRR1)
.......................................................... 319
ELVR
Detection Level Setting Register (ELVR1) ......... 323
Enable Sector Protect
Enable Sector Protect/verify Sector Protect ......... 642
ENIR
DTP/External Interrupt Enable Register (ENIR1)
.......................................................... 321
Erase
Detailed Explanation of Flash Memory Write/erase
.......................................................... 544
Erasing
Erasing All Data in the Flash Memory (erasing chips)
.......................................................... 548
Erasing Chip
Erasing All Data in the Flash Memory (erasing chips)
.......................................................... 548
Erasing Chip in the Flash Memory ..................... 548
ESCR
Extended Status/control Register (ESCR) ........... 401
Evaluation Chip
Block Diagram of Evaluation Chip ........................ 9
Event Count Mode
Event Count Mode ........................................... 238
Operation in Event Count Mode ........................ 261
Setting of Event Count Mode ............................ 259
Event Counter Mode
Program Example in Event Counter Mode .......... 264
Exceptions
Exceptions ......................................................... 58
Extended Communication Control Register
Extended Communication Control Register (ECCR)
.......................................................... 403
Extended Intelligent I/O Service
Extended Intelligent I/O Service (EI
2
OS) ....... 57, 74
Extended Intelligent I/O Service Descriptor (ISD)
............................................................ 76
Extended Status/control Register
Extended Status/control Register (ESCR) ........... 401
External Clock
Connection of an Oscillator or an External Clock
to the Microcontroller ..........................108
External Interrupt
Block Diagram of DTP/External Interrupt ...........315
DTP/External Interrupt Enable Register (ENIR1)
..........................................................321
DTP/External Interrupt Factor Register (EIRR1)
..........................................................319
DTP/External Interrupt Function ........................314
DTP/External Interrupt Operation ......................329
External Interrupt Function ................................331
List of Registers and Reset Values in DTP/
External Interrupt .................................318
Pins of DTP/External Interrupt ...........................317
Precautions when Using DTP/External Interrupt
..........................................................333
Program Example of DTP/External Interrupt Function
..........................................................335
Selection of External Interrupt Factor .................325
Setting of DTP/External Interrupt .......................327
External Reset
Block Diagrams of the External Reset Pin ...........125
External Single Clock
Sub-clock Mode with External Single Clock Product
..........................................................116
F
F
2
MC-16LX
F
2
MC-16LX Instruction List ..............................600
Features
Features ...............................................................7
FF Bank
Access to FF Bank by ROM Mirroring Function
..........................................................526
Flag Change Disable Prefix
Flag Change Disable Prefix (NCC) .......................49
Flag Set Timing
Reception Interrupt Generation and Flag Set Timing
..........................................................409
Transmission Interrupt Generation and Flag Set
Timing ................................................411
Flash
Block Diagram of Flash/Mask ROM Version ........11
Flash Memory
512K-bit Flash Memory Features .......................530
Block Diagram of the Entire Flash Memory ........531
Detailed Explanation of Flash Memory Write/erase
..........................................................544
Erasing All Data in the Flash Memory (erasing chips)
..........................................................548
Erasing Chip in the Flash Memory .....................548
Flash Memory Control Signals ...........................533
Notes on Using Flash Memory ...........................550