FUJITSU F2MCTM-16LX - Manual (Page 173)

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CHAPTER 8 LOW-POWER CONSUMPTION MODE
8.8 Usage Notes on Low-Power Consumption Mode
This section explains the notes when using the low-power consumption modes.
■ Transition to Standby Mode
When an interrupt request is generated from the resource to the CPU, the mode does not transit to each
standby mode even after setting the STP and SLP bits to 1 and the TMD bit to 0 in the low-power
consumption mode control register (LPMCR) (and also even after interrupt processing).
If the CPU is servicing an interrupt, the interrupt-service-time interrupt request flag is cleared and the CPU
can enter the standby mode unless any other interrupt request has been generated.
■ Notes on the Transition to Standby Mode
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode,
watch mode, or timebase timer mode, use the following procedure:
1. Disable the output of peripheral functions.
2. Set the SPL bit to "1", STP bit to "1", or TMD bit to "0" in the low-power consumption mode control
register (LPMCR).
■ Cancellation of Standby Mode by Interrupt
When an interrupt request higher than the interrupt level (IL) of 7 is generated from the resource and
external interrupt during operation in the sleep mode, watch mode, timebase timer mode, or stop mode, the
standby mode is cancelled. The standby mode is cancelled by an interrupt regardless of whether the CPU
accepts interrupts or not.
Note:
To prevent the CPU from causing a branch to interrupt servicing immediately after returning from
standby mode, take measures, such as disabling interrupts before setting the standby mode.
■ Note on Canceling Standby Mode
The standby mode can be cancelled by an input according to the settings of an input factor of an external
interrupt. The input factor can be selected from High level, Low level, rising edge, and falling edge.
■ Oscillation Stabilization Wait Time
●
Oscillation stabilization wait time of main clock
In the sub clock mode, watch mode, or stop mode, the oscillation of the main clock stops and the oscillation
stabilization wait time of the main clock is required. The oscillation stabilization wait time of the main
clock is set by the WS1 and WS0 bits in the clock selection register (CKSCR).
●
Oscillation stabilization wait time of sub clock
In the sub-stop mode, the oscillation of the sub clock (SCLK) stops and the oscillation stabilization wait
time of the sub clock is required. The oscillation stabilization wait time of the sub clock is fixed at 2
14
/
SCLK (SCLK: sub clock).