4 pll/subclock control register (psccr), Pll/subclock control register (psccr) – FUJITSU F2MCTM-16LX User Manual
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CHAPTER 5 CLOCKS
5.4
PLL/Subclock Control Register (PSCCR)
PLL/Subclock control register selects the PLL multiplication rate and subclock division
rate. This register is write only. Read value of all bits is set to "1".
■
Configuration of the PLL/Subclock Control Register (PSCCR)
Figure 5.4-1 shows the configuration of the PLL/Subclock control register (PSCCR). Table 5.4-1 shows the
function of each bit in the PLL/subclock control register (PSCCR).
Figure 5.4-1 Configuration of the PLL/Subclock Control Register (PSCCR)
Address
15
14
13
12
11
10
9
8
Reset value
0000CF
H
−
−
−
−
Re-
served
SCDS
Re-
served
CS2
XXXX0000
B
−
−
−
−
W
W
W
W
W
: Write only
X
: Undefined
−
: Unused
: Initial value
bit8
CS2
Multiplication rate selection bit
0
See the clock selection register
(CKSCR).
1
bit9
Reserved
Reserved bit
0
Always write "0" to this bit.
Read value is always "1".
bit10
SCDS
Subclock division selection bit
0
4 division
1
2 division
bit11
Reserved
Reserved bit
0
Always write "0" to this bit.
Read value is always "1".